EITF35 Digitala strukturer på kisel
Teaching Assistants & Approval:
Note that all TAs can help you for each lab, so don't be shy and ask away. But ONLY the dedicated TA can approve you in the labs, as follows:
|Lab 1||Mohammad Attari (MA)|
|Lab 2||Masoud Nouripayam (MN)|
|Lab 3||Arturo Prieto (AP)|
|Labs 4 & 5||Lucas Ferreira (LF), Jesús Rodríguez (JR)|
Note: Each TA will be available ONLY in 50% of each lab session.
Check here: TA Schedule (updated)
Please read the checklist and prepare the requirements BEFORE asking for approval.
Assignment 4 and 5:
You can choose from one of the following two tracks (or propose your own project, if you feel more adventurous):
1) VGA + CORDIC
When using the reference design, the coe file for the ROM needs to be pointed to the correct location before synthesis. The location of the coe file is
instead of IEEE.NUMERIC_STD.ALL to maintain compatibility with the VGA reference design
2) Machine learning
Update: 10/October/2019: Check out this nice explanation of what is and how to do a multidimensional convolution: (https://towardsdatascience.com/a-comprehensive-introduction-to-different-types-of-convolutions-in-deep-learning-669281e58215)
Biases for Fully connected layers are:
FC1: signed("110100"), signed("010100"), signed("011000");
- A few slides on Questasim are here.
- A few slides on using Xilinx Vivado are here.
- An example project for using Xilinx IP generators and ILA can be downloaded here.
NOTE: If you have logged in the first time using your account, you might have problems accessing licences. Log off and log back in and it should fix the problem.
NOTE: Create your Vivado projects inside C:\Users\login-id\Program\YOUR_DIRECTORY where YOUR_DIRECTORY is the directory where you save all your work