Övningar
For each lecture, there is a related problem solving session. Below is a list of recommended problems to each problem solving session. Solutions to all exercises are available in this PDF.
There are two teaching assistants in the course: Linus Karlsson and Erik Mårtensson. Linus will teach the mixed D/E sessions in the schedule, and Erik will teach those that are exclusively D or E. You are welcome to attend any session you want to.
"🎥" means that this exercise has related Youtube walkthroughs. See the bottom of this page for links.
NOTE a schedule change: Tuesdays 10-12 seem more popular than 8-10. Thus, instead of two parallel classes 8-10, we move one of them to 10-12. I clear text:
- 2/10: 8-10 in E:4115 is moved to 10-12 in E:4115
- 9/10: 8-10 in E:4115 is moved to 10-12 in E:4115
- 16/10: 8-10 in E:4115 is moved to 10-12 in E:2311 (<---- Note the room change)
The TimeEdit schedule has now been updated to reflect the changes as well.
HT 1
Lecture |
Part | Topic |
Problems |
1 | 2.2 | Introduction | 2.1-2.4 Exercises |
2 | 2.1-2.2 | Finite state machines | 2.5, 2.6, 2.8, 2.12, 2.13 Övningsanteckningar |
3 | 2.3 | Sequential circuits | 2.16a, 2.17, 2.19, 2.20, 2.23, 2.26 |
4 | 3.1-3.3 | Computing with integers and algebraic structures 🎥 | 3.1-3.5, 3.7, 3.8, 3.11, (3.13) |
5 | 3.3, 4.5 | Boolean algebra and Arithmetics | 3.21-3.24, 3.28, 4.18-4.20 |
6 | 4.1-4.3.3 | Boolean functions and normal forms | 4.1, 4.3, 4.5-4.6 Övningsanteckningar |
7 | 5.1.1-5.1.2 | Minimal functions 🎥 | 5.1b, 5.2b, 5.4-5.6 |
8 | 5.1.2 | Karnaugh maps 🎥 | 5.8ab, 5.9, 5.11, 5.13b, 5.14e |
9 | 6.1 | State minimisation 🎥 | 6.1 |
10 | 6.2 | State assignment | 6.5-6.7 RD-algoritmen: s1 s2 |
11 | 6.3, 6.4, 5.3 | Asynchronous seq.circ. and Mealy-Moore 🎥 | 6.3, 6.4, 6.11, 6.12, 6.14 |
12 | 5.4 | Standard components and gates on transistor level | |
13 | 7.1-7.2 | Linear circuits 🎥 | 5.21a, 7.1-7.4, 7.7 |
14 | 7.2-7.3 | D-transform and LFSR | 7.13, 7.14, 7.6, 7.12, 7.15, 7.17, 7.19 |
N/A | Almost everything | Neat assignments that covers large parts of HT 1. Perfect to exercise large parts of the course! | 6.16, 6.17, 6.22-6.24, 5.21b-e |
HT 2
Lecture | Part | Topic |
Problems |
15 | Introduction to VHDL | Appendix B in the manual for the laboratory exercises. | |
16 | Combinational logic with VHDL |
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17 |
Sequential logic with VHDL |
Exercise 3, VHDL files | |
18 |
Question hours lab 4 |
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19 |
Question hours lab 5/6 | ||
20 |
Question hours lab 5/6 | ||
21 |
Julmys med övningsledarna (or ask about lab 5/6) |
Youtube videos
Playlist of all videos in the course
- Euclid's algorithm
- Bézout's identity
- Euclid's extended algorithm
- Multiplicative inverse (unit)
- Iterative consensus
- Karnaugh map, small example
- Karnaugh map, larger example
- State minimisation (RF-algorithm)
- Asynchronous seq. circuits
- Reduced form of linear sequential circuits
These videos are fairly new (2017 and 2018), if you have any comments, suggestions, complaints, or just thoughts about life in general, contact Linus.