Electrical and Information Technology

Faculty of Engineering LTH | Lund University

Course Programme

EITF20 Computer Architecture, 2019/2020


Detailed schedule can be found here.

Schedule (the schedule is preliminary, can subject to changes during the course):

2019-11-05: Performance, Quantitative principles; HP Ch. 1 (slides)

2019-11-07: Instruction set architectures, ISA; HP Ch. 1.3, App. A (slides); 

2019-11-12: Pipelining I; HP App. C.1-C.5 (slides)

2019-11-14: Pipelining II; HP App. C.6-C.7, C.2, Ch. 3.1-3.2, 3.9 (slides)

2019-11-19: Pipelining III; HP Ch. 3.4-3.8,3.10-3.11 (slides)

2019-11-21: Memory systems, cache I; HP Ch 2.1, App. B.1-B.2 (slides)

2019-11-26: Exercise I, Solutions, Excel Sheet

2019-11-28: Buffer to handle the delay

2019-12-03: Memory systems, cache II; HP Ch. 2.2-2.3, App. B.3 (slides)

2019-12-05: Memory systems, virtual memory; HP App B.4, Ch. 2.5-2.6 (slides)

2019-12-10: Multi-core HP App D, Ch. 5.1-5.2 (slides);

2019-12-12: Application-specific processors (slides)

2019-12-17: Exercise II, Solutions

2019-12-19: Invited Lecture


You need to sign up for the labs via the Sign up page in the menu to the left! (Rooms E:4118, E:4119)

There are 4 laboratories:

Lab 1 : Pipelined processors (Week 47) 

Lab 2 : Advanced pipelining (Week 48) 

Lab 3 : Cache memory (Week 49) 

Lab 4 : Advanced cache, cache coherence (Week 50) 


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