Laborationer
If the door to the lab room 4121 is closed you can open the lab room 4118 which has a card reader and go from there to 4121.
A few slides on Questasim are here.
A few slides on using Xilinx Vivado are here.
An example project for using Xilinx IP generators and ILA can be downloaded here.
NOTE: If you have logged in the first time using your account, you might have problems accessing licences. Log off and log back in and it should fix the problem.
NOTE: Create your Vivado projects inside C:\Users\login-id\Program\YOUR_DIRECTORY where YOUR_DIRECTORY is the directory where you save all your work
Assignment 1: Sequence Detector, Mind the deadlines! (Testfiles Sequence) (updated: 5/09 16.00)
Assignment 2: Keyboard Controller (Presentation, Lab_Manual, VHDLfiles)
Assignment 3: ALU (Presentation, Lab_Manual, VHDL Files, Modulo3)
Assignment 4 and 5: Calculator with memory and VGA display. (Lab manual, Matlab Files, CORDIC Intro, reporttemplate) Note: Lab 5 is now up-to-date
NOTE: When using the reference design, the coe file for the ROM needs to be pointed to the correct location before synthesis. The location of the coe file is "YOUR_PJT\VGA_REF_DESIGN\VGA_REF_DESIGN.srcs\sources_1\imports\vhdl\ip_core\welcome_480x120.coe"
NOTE: LAB4 and LAB5
Please use
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
instead of IEEE.NUMERIC_STD.ALL to maintain compatibility with the VGA reference design
NOTE: We will have lab sessions next week (Oct. 18- Oct. 20) like previous weeks.
Please read the checklist file for each lab and prepare the requirements. Always look at this file before the labs for the new updates (last update: Sept. 18).