Kursprogram
Lectures
Tuesdays 13-15 and Thursdays 8-10 in E:1406 (except for First lecture Tuesday 2015-11-03, 13.15-15.00, E:B)
Use HP book 5th Edition
Detailed schedule can be found here:
Schedule:
- 2015-11-03: Performance, Quantitative principles; HP Ch. 1 (slides)
- 2015-11-10: Instruction set architectures, ISA; HP Ch. 1.3, App. A (slides); Article: , "GPU vs. CPU Computing"
- 2015-11-12: Pipelining I; HP App. C.1-C.5 (slides)
- 2015-11-17: Pipelining II; HP App. C.6-C.7, C.2, Ch. 3.1-3.2, 3.9 (slides)
- 2015-11-19: Pipelining III; HP Ch. 3.4-3.8,3.10-3.11 (slides)
- 2015-11-24: Memory systems, cache I; HP Ch 2.1, App. B.1-B.2 (slides)
- 2015-11-26: Memory systems, cache II; HP Ch. 2.2-2.3, App. B.3 (slides)
- 2015-12-01: Memory systems, virtual memory; HP App B.4, Ch. 2.5-2.6 (slides)
- 2015-12-03: Storage Systems, I/O; HP App D (slides)
- 2015-12-08: Course summary (slides);
A good overview of Computer Architecture: Jason Patterson, "Modern Microprocessors - A 90 Minute Guide"
Question hours (frågetimmar)
- Monday Dec 17, 10-12, E:1406
Laboratories
There are 4 laboratories
You need to sign up for the labs via the 'Sign up' page in the menu to the left! (Rooms E:4115, E:4118, E:4119)
- (Week 47) Pipelined processors.
- (Week 48) Advanced pipelining.
- (Week 49) Cache memory.
- (Week 50) Advanced cache, tradeoffs.
Assessment
Examination through approved labs followed by a successful written examination