Laborationer
# Make sure you don't distribute any files located in below-mentioned paths
- To run any digital tool required for asic implementation flow, create a project folder in your home directory, open a terminal in that folder and type the following in the opened terminal:
source /usr/local-eit/cad2/cmpstm/stm065v536/setup2020.efd
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DesignKit Files can be accessed from following path:
/usr/local-eit/cad2/cmpstm/stm065v536
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All necessary files regarding the project can be found in the following path:
/usr/local-eit/cad2/cmpstm/dicp18
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A dummy design can be found in :
/usr/local-eit/cad2/cmpstm/dicp18/Dummy_Design
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The matrix multiplication function model and stimuli file can be found here
- Regarding SRAM:
- SRAM can be accessed from (SRAM size: 160 Words x 32bits):
/usr/local-eit/cad2/cmpstm/mem2011/SPHD110420-48158@1.0
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- For Functional/timing simulation (here using modelsim) you need to compile the verilog model of memory (/usr/local-eit/cad2/cmpstm/mem2011/SPHD110420-48158@1.0/behaviour/verilog/SPHD110420.v)
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For the synthesis and Place and Route you just need *.db, *.lib, *.lef depending on the tool
Asic Simulation
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To learn how to use modelsim, a simple google search gives you abundace of tutorials to go through
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Modelsim can be access using command: vsim &
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To enable some extra debugging options in modelsim use command: vsim -debugDB
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If you look for having modelsim simultor on your own laptop see this link for downloading student version
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Please look at the documentation to learn how to develop your design considering the memory: /usr/local-eit/cad2/cmpstm/mem2011/SPHD110420-48158@1.0/doc/C65LP_ST_SPHDL_BE/UserManual/C65LP_ST_SPHDL_BE.pdf
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A good practice is to write a testbench just for the memory (you have access to memory IO pins through the mem wrapper) to learn about its timing
Synthesis
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Genus (Cadence synthesis tool) can be accessed by 'genus' command (To run the Genus in legacy_ui to access synthesis environment attributes type genus -legacy_ui)
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To show the graphical user interface (gui) use: gui_show
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If you end up being in common_ui environment (genus@root:>), type:
- ::legacy::set_attribute common_ui false /
- ::legacy::set_attribute common_ui false /
- Synthesis Lecture Slides is here
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For a better understanding of Technology files see this
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Remember NOT to include the behavorial file of the memory while performing synthesis (include only .lib files)
Place and Route
- To run PNR tool, Using terminal go to your project dir, run initialization command and afterwards type: encounter
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To be able to continue with next step you need a top module including the physical IO pads. Write your own top module with pads, and synthesize it with the tool to make a netlist including pads
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You should create an IO assignment file before being able to proceed further with PNR tool. Check /usr/local-eit/cad2/cmpstm/dicp18/Dummy_Design/soc/MEDIANFILTER.io to get an understanding about IO assignment
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Place & Route Lecture slides here (a brief explanation on what exactly PNR means)
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Backend Flow Slides here
Power Analysis
- Slides for PrimeTime is here
- Sample script for power analysis in PrimeTime