Laborationer
If the door to the lab room 4121 is closed you can open the lab room 4118 which has a card reader and go from there to 4121.
Make sure you change your password when you log in the first time!
A few slides on Questasim are here.
A few slides on using Xilinx Vivado are here.
An example project for using Xilinx IP generators and ILA can be downloaded here.
We will have a tutorial on VIVADO Friday.
NOTE: If you have logged in the first time using your account, you might have problems accessing licences. Log off and log back in and it should fix the problem.
Also, there might be issues when the vivado project is in U: drive, its better to have the project in local C drive.
Assignment 1: Sequence Detector, Mind the deadlines! (Test files Sequence)
Assignment 2: Keyboard Controller (Presentation, Lab_Manual, VHDL files)
The Lab2 deadline is on Friday 25-th 5 PM, and note that there is no need to hand-over pre-work for Lab2.
Assignment 3: ALU (Lab_Manual, VHDL skeleton)
Assignment 4 and 5: Calculator with memory and VGA display. (Lab manual, slides, Reference Design)
NOTE: When using the reference design, the coe file for the ROM needs to be pointed to the correct location before synthesis. The location of the coe file is "YOUR_PJT\VGA_REF_DESIGN\VGA_REF_DESIGN.srcs\sources_1\imports\vhdl\ip_core\welcome_480x120.coe"