Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
date_generatedMon Oct 05 11:45:04 2015 product_versionVivado v2014.4 (64-bit)
build_version1071353 os_platformWIN64
registration_id202989797_177879404_210593006_625 tool_flowVivado
betaFALSE route_designTRUE
target_familyartix7 target_devicexc7a100t
target_packagecsg324 target_speed-1
random_idd75675afa85d550a8d2662e0cd123bfc project_id722fe8fc5e2944eaaebbe65fa6d238ff
project_iteration0

user_environment
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
cpu_nameIntel(R) Core(TM) i5-3570 CPU @ 3.40GHz cpu_speed3399 MHz
total_processors1 system_ram8.000 GB

vivado_usage
project_data
srcsetcount=6 constraintsetcount=1 designmode=RTL prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=Vivado Synthesis Defaults implstrategy=Vivado Implementation Defaults currentsynthesisrun=synth_1 currentimplrun=impl_1
totalsynthesisruns=3 totalimplruns=3

unisim_transformation
pre_unisim_transformation
bufg=2 carry4=4 fdce=16 fdre=30
gnd=9 ibuf=2 lut1=2 lut2=7
lut3=21 lut4=10 lut5=9 lut6=29
mmcme2_adv=1 obuf=14 ramb36e1=6 vcc=7
post_unisim_transformation
bufg=2 carry4=4 fdce=16 fdre=30
gnd=9 ibuf=2 lut1=2 lut2=7
lut3=21 lut4=10 lut5=9 lut6=29
mmcme2_adv=1 obuf=14 ramb36e1=6 vcc=7

placer
usage
lut=66 ff=44 bram36=6 bram18=0
ctrls=4 dsp=0 iob=16 bufg=0
global_clocks=2 pll=0 bufr=0 nets=187
movable_instances=165 pins=2163 bogomips=0 effort=2
threads=2 placer_timing_driven=1 timing_constraints_exist=1 placer_runtime=1.466000

power_opt_design
usage
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=44 srls_augmented=0
srls_newly_gated=0 srls_total=0 bram_ports_augmented=0 bram_ports_newly_gated=0
bram_ports_total=12 flow_state=default
command_line_options_spo
-clocks=default::[not_specified] -include_cells=default::[not_specified] -exclude_cells=default::[not_specified] -cell_types=default::all

ip_statistics
blk_mem_gen_v8_2/1
iptotal=1 x_ipproduct=Vivado 2014.4 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=blk_mem_gen x_ipversion=8.2 x_ipcorerevision=3 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=artix7 c_xdevicefamily=artix7 c_elaboration_dir=./
c_interface_type=0 c_axi_type=1 c_axi_slave_type=0 c_use_bram_block=0
c_enable_32bit_address=0 c_ctrl_ecc_algo=NONE c_has_axi_id=0 c_axi_id_width=4
c_mem_type=3 c_byte_size=9 c_algorithm=1 c_prim_type=1
c_load_init_file=1 c_init_file_name=[user-defined] c_init_file=rom_welcome.mem c_use_default_data=1
c_default_data=0 c_has_rsta=0 c_rst_priority_a=CE c_rstram_a=0
c_inita_val=0 c_has_ena=0 c_has_regcea=0 c_use_byte_wea=0
c_wea_width=1 c_write_mode_a=WRITE_FIRST c_write_width_a=3 c_read_width_a=3
c_write_depth_a=65536 c_read_depth_a=65536 c_addra_width=16 c_has_rstb=0
c_rst_priority_b=CE c_rstram_b=0 c_initb_val=0 c_has_enb=0
c_has_regceb=0 c_use_byte_web=0 c_web_width=1 c_write_mode_b=WRITE_FIRST
c_write_width_b=3 c_read_width_b=3 c_write_depth_b=65536 c_read_depth_b=65536
c_addrb_width=16 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_mux_pipeline_stages=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0
c_use_softecc=0 c_use_ecc=0 c_en_ecc_pipe=0 c_has_injecterr=0
c_sim_collision_check=ALL c_common_clk=0 c_disable_warn_bhv_coll=0 c_en_sleep_pin=0
c_disable_warn_bhv_range=0 c_count_36k_bram=6 c_count_18k_bram=0 c_est_power_summary=Estimated Power for IP _ 6.44925 mW
clk_wiz_v5_1/1
iptotal=1 component_name=clk_wiz_0 use_phase_alignment=true use_min_o_jitter=false
use_max_i_jitter=false use_dyn_phase_shift=false use_inclk_switchover=false use_dyn_reconfig=false
enable_axi=0 feedback_source=FDBK_AUTO primitive=MMCM num_out_clk=1
clkin1_period=10.0 clkin2_period=10.0 use_power_down=false use_reset=true
use_locked=true use_inclk_stopped=false feedback_type=SINGLE clock_mgr_type=NA
manual_override=false

report_power
command_line_options
-verbose=default::[not_specified] -hier=default::power -no_propagation=default::[not_specified] -format=default::text
-file=[specified] -name=default::[not_specified] -xpe=default::[not_specified] -return_string=default::[not_specified]
-vid=default::[not_specified] -append=default::[not_specified] -l=default::[not_specified]
usage
customer=TBD customer_class=TBD flow_state=routed family=artix7
die=xc7a100tcsg324-1 package=csg324 speedgrade=-1 version=2014.4
platform=nt64 temp_grade=commercial process=typical simulation_file=None
netlist_net_matched=NA pct_clock_constrained=0.000000 pct_inputs_defined=50 user_junc_temp=26.0 (C)
ambient_temp=25.0 (C) user_effective_thetaja=4.6 airflow=250 (LFM) heatsink=medium (Medium Profile)
user_thetasa=4.6 (C/W) board_selection=medium (10"x10") board_layers=12to15 (12 to 15 Layers) user_thetajb=5.7 (C/W)
user_board_temp=25.0 (C) junction_temp=26.0 (C) input_toggle=12.500000 output_toggle=12.500000
bi-dir_toggle=12.500000 output_enable=1.000000 bidir_output_enable=1.000000 output_load=5.000000
ff_toggle=12.500000 ram_enable=50.000000 ram_write=50.000000 dsp_output_toggle=12.500000
set/reset_probability=0.000000 enable_probability=0.990000 toggle_rate=False signal_rate=False
static_prob=False read_saif=False on-chip_power=0.215879 dynamic=0.118160
effective_thetaja=4.6 thetasa=4.6 (C/W) thetajb=5.7 (C/W) off-chip_power=0.000000
clocks=0.000316 logic=0.000042 signals=0.000019 bram=0.002701
mmcm=0.115009 i/o=0.000073 devstatic=0.097719 vccint_voltage=1.000000
vccint_total_current=0.018435 vccint_dynamic_current=0.003007 vccint_static_current=0.015428 vccaux_voltage=1.800000
vccaux_total_current=0.082001 vccaux_dynamic_current=0.063836 vccaux_static_current=0.018165 vcco33_voltage=3.300000
vcco33_total_current=0.004002 vcco33_dynamic_current=0.000002 vcco33_static_current=0.004000 vcco25_voltage=2.500000
vcco25_total_current=0.000000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco18_voltage=1.800000
vcco18_total_current=0.000000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco15_voltage=1.500000
vcco15_total_current=0.000000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco135_voltage=1.350000
vcco135_total_current=0.000000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco12_voltage=1.200000
vcco12_total_current=0.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vccaux_io_voltage=1.800000
vccaux_io_total_current=0.000000 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccbram_voltage=1.000000
vccbram_total_current=0.000634 vccbram_dynamic_current=0.000240 vccbram_static_current=0.000394 mgtavcc_voltage=1.000000
mgtavcc_total_current=0.000000 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavtt_voltage=1.200000
mgtavtt_total_current=0.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 vccadc_voltage=1.800000
vccadc_total_current=0.020000 vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 confidence_level_design_state=High
confidence_level_clock_activity=High confidence_level_io_activity=Medium confidence_level_internal_activity=Medium confidence_level_device_models=High
confidence_level_overall=Medium

report_utilization
slice_logic
slice_luts_used=66 slice_luts_fixed=0 slice_luts_available=63400 slice_luts_util_percentage=0.10
lut_as_logic_used=66 lut_as_logic_fixed=0 lut_as_logic_available=63400 lut_as_logic_util_percentage=0.10
lut_as_memory_used=0 lut_as_memory_fixed=0 lut_as_memory_available=19000 lut_as_memory_util_percentage=0.00
slice_registers_used=44 slice_registers_fixed=0 slice_registers_available=126800 slice_registers_util_percentage=0.03
register_as_flip_flop_used=44 register_as_flip_flop_fixed=0 register_as_flip_flop_available=126800 register_as_flip_flop_util_percentage=0.03
register_as_latch_used=0 register_as_latch_fixed=0 register_as_latch_available=126800 register_as_latch_util_percentage=0.00
f7_muxes_used=0 f7_muxes_fixed=0 f7_muxes_available=31700 f7_muxes_util_percentage=0.00
f8_muxes_used=0 f8_muxes_fixed=0 f8_muxes_available=15850 f8_muxes_util_percentage=0.00
slice_used=18 slice_fixed=0 slice_available=15850 slice_util_percentage=0.11
slicel_used=10 slicel_fixed=0 slicem_used=8 slicem_fixed=0
lut_as_logic_used=66 lut_as_logic_fixed=0 lut_as_logic_available=63400 lut_as_logic_util_percentage=0.10
using_o5_output_only_used=0 using_o5_output_only_fixed= using_o6_output_only_used=55 using_o6_output_only_fixed=
using_o5_and_o6_used=11 using_o5_and_o6_fixed= lut_as_memory_used=0 lut_as_memory_fixed=0
lut_as_memory_available=19000 lut_as_memory_util_percentage=0.00 lut_as_distributed_ram_used=0 lut_as_distributed_ram_fixed=0
lut_as_shift_register_used=0 lut_as_shift_register_fixed=0 lut_flip_flop_pairs_used=66 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_available=63400 lut_flip_flop_pairs_util_percentage=0.10 fully_used_lut_ff_pairs_used=35 fully_used_lut_ff_pairs_fixed=
lut_ff_pairs_with_unused_lut_used=0 lut_ff_pairs_with_unused_lut_fixed= lut_ff_pairs_with_unused_flip_flop_used=31 lut_ff_pairs_with_unused_flip_flop_fixed=
unique_control_sets_used=4 minimum_number_of_registers_lost_to_control_set_restriction_used=12(Lost)
memory
block_ram_tile_used=6 block_ram_tile_fixed=0 block_ram_tile_available=135 block_ram_tile_util_percentage=4.44
ramb36_fifo*_used=6 ramb36_fifo*_fixed=0 ramb36_fifo*_available=135 ramb36_fifo*_util_percentage=4.44
ramb36e1_only_used=6 ramb18_used=0 ramb18_fixed=0 ramb18_available=270
ramb18_util_percentage=0.00
dsp
dsps_used=0 dsps_fixed=0 dsps_available=240 dsps_util_percentage=0.00
clocking
bufgctrl_used=2 bufgctrl_fixed=0 bufgctrl_available=32 bufgctrl_util_percentage=6.25
bufio_used=0 bufio_fixed=0 bufio_available=24 bufio_util_percentage=0.00
mmcme2_adv_used=1 mmcme2_adv_fixed=0 mmcme2_adv_available=6 mmcme2_adv_util_percentage=16.66
plle2_adv_used=0 plle2_adv_fixed=0 plle2_adv_available=6 plle2_adv_util_percentage=0.00
bufmrce_used=0 bufmrce_fixed=0 bufmrce_available=12 bufmrce_util_percentage=0.00
bufhce_used=0 bufhce_fixed=0 bufhce_available=96 bufhce_util_percentage=0.00
bufr_used=0 bufr_fixed=0 bufr_available=24 bufr_util_percentage=0.00
specific_feature
bscane2_used=0 bscane2_fixed=0 bscane2_available=4 bscane2_util_percentage=0.00
capturee2_used=0 capturee2_fixed=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_fixed=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_fixed=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_fixed=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_fixed=0 icape2_available=2 icape2_util_percentage=0.00
pcie_2_1_used=0 pcie_2_1_fixed=0 pcie_2_1_available=1 pcie_2_1_util_percentage=0.00
startupe2_used=0 startupe2_fixed=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=0 xadc_fixed=0 xadc_available=1 xadc_util_percentage=0.00
primitives
lut6_used=29 lut6_functional_category=LUT fdre_used=28 fdre_functional_category=Flop & Latch
lut3_used=21 lut3_functional_category=LUT fdce_used=16 fdce_functional_category=Flop & Latch
obuf_used=14 obuf_functional_category=IO lut4_used=10 lut4_functional_category=LUT
lut5_used=9 lut5_functional_category=LUT ramb36e1_used=6 ramb36e1_functional_category=Block Memory
lut2_used=6 lut2_functional_category=LUT carry4_used=4 carry4_functional_category=CarryLogic
lut1_used=2 lut1_functional_category=LUT ibuf_used=2 ibuf_functional_category=IO
bufg_used=2 bufg_functional_category=Clock mmcme2_adv_used=1 mmcme2_adv_functional_category=Clock
io_standard
blvds_25=0 lvcmos33=1 sstl15_r=0 lvttl=0
diff_sstl15=0 hstl_ii=0 diff_mobile_ddr=0 lvcmos25=0
diff_sstl18_ii=0 hstl_i=0 mobile_ddr=0 lvcmos12=0
sstl135_r=0 lvcmos15=0 lvcmos18=0 pci33_3=0
hsul_12=0 hstl_i_18=0 diff_hsul_12=0 hstl_ii_18=0
sstl18_i=0 sstl18_ii=0 sstl15=0 sstl135=0
lvds_25=0 diff_hstl_i=0 rsds_25=0 diff_hstl_ii=0
tmds_33=0 diff_hstl_i_18=0 mini_lvds_25=0 diff_hstl_ii_18=0
ppds_25=0 diff_sstl18_i=0 diff_sstl15_r=0 diff_sstl135=0
diff_sstl135_r=0

router
usage
lut=68 ff=44 bram36=6 bram18=0
ctrls=4 dsp=0 iob=16 bufg=0
global_clocks=2 pll=0 bufr=0 nets=187
movable_instances=165 pins=2163 bogomips=0 high_fanout_nets=0
effort=2 threads=2 router_timing_driven=1 timing_constraints_exist=1
congestion_level=0 estimated_expansions=141372 actual_expansions=459024 router_runtime=29.847000

synthesis
command_line_options
-part=xc7a100tcsg324-1 -name=default::[not_specified] -top=vga_ref -include_dirs=default::[not_specified]
-generic=default::[not_specified] -verilog_define=default::[not_specified] -constrset=default::[not_specified] -seu_protect=default::none
-flatten_hierarchy=default::rebuilt -gated_clock_conversion=default::off -directive=default::default -rtl=default::[not_specified]
-bufg=default::12 -fanout_limit=default::10000 -shreg_min_size=default::3 -mode=default::default
-fsm_extraction=default::auto -keep_equivalent_registers=default::[not_specified] -resource_sharing=default::auto -control_set_opt_threshold=default::auto
usage
elapsed=00:00:23s memory_peak=566.094MB memory_gain=385.465MB hls_ip=0