Godkända
Verktyg för Hög Nivå Syntes för Paket Processning med Hög Hastighet
Venkata Soumya Pakki (2010) och Yian Wang (2010)
Start
2012-06-01
Presentation
2014-08-28
Plats:
Avslutat:
2014-08-28
Examensrapport:
Sammanfattning
The main objective of this Master Thesis is to design and implement a high level synthesis tool for high speed packet processing. Packet processing is responsible for the traversal of packets/frames between the three layers (data link,network,transport) of OSI model. For a given network packet, determining the destination and performing the required alterations to the packet are the key parts of Packet Processing. Due to the regularity of packet processing, a high level program can be designed to describe the processing instead of hardware description language. The instructions that are needed for packet processing will be defined and RTL design of basic and advanced instructions will be implemented. Verilog will be used to implement the RTL of the project. Verification is done for the designed RTL model. Another part of the project is to design the optimized program. For instance, optimization is done to run as much code as possible in parallel or for removal of unused hardware at each pipeline stage. Using Python, the instructions program is translated into RTL model. The RTL implementation and verification is done for the optimized instructions program. The aim is to be able to build a compiler and generate a timeless executable model and a synthesizable RTL model.
Handledare: Robert Wikander (Packet Architects AB)
Examinator: Viktor Öwall (EIT)