Godkända
Low-power Microprocessor based on Stack Architecture
Girish Aramanekoppa Subbarao ()
Start
2015-02-02
Presentation
2015-06-01
Plats:
E:3139
Avslutat:
2015-09-16
Examensrapport:
Sammanfattning
There are many applications of microprocessors in embedded applications, where power efficiency becomes a critical requirement, e.g. wearable or mobile devices in healthcare, space instrumentation and hand-held devices. One of the methods of achieving low power operation is by simplifying the device architecture. RISC/CISC processors consume more power because of their complexity, which is due their multiplexer system connecting the register le to the functional units and their instruction pipeline system. On the other hand, the Stack machines are comparatively less complex due to their implied addressing to the top two registers of the stack and smaller operation codes. This makes the instruction and the address decoder circuit simple by eliminating the multiplex switches for read and write ports of the register file. They are also optimized for procedure calls because they operate on stack instead of register, which reduces the memory size. All these factors make a stack machine power-efficient. In this thesis project a Stack-based processor was designed in 65nm CMOS technology. The processor core is extremely compact with the size of 0.12 mm2. The processor is powered by 1.2V DC and consumes about 80 uW/MHz, which is less than typical 250 to 450 uW/MHz consumed by the commercially produced low-power microcontrollers. This device was tested up to a speed of 50 MHz.
Handledare: Anders Ardö (EIT)
Examinator: Joachim Rodrigues (EIT)