Godkända
Clock tree design in sub-Vt circuits - Analysis on standard- and full-custom gates
Yuqi Liu ()
Start
2012-10-21
Presentation
2013-06-19 10:15
Plats:
Avslutat:
2013-06-19
Examensrapport:
Sammanfattning
Process variation at the subthreshold (sub-VT) region is a key factor that aects the functionality of a clock tree. Standard-cell clock buers experience more performance variation among dierent design corners than that in the nominal supply voltage (VDD). This variation eect should thus be reduced. In this report, some aspects of constructing clock tree for sub-VT operation has been studied and compared. It has been conrmed that performing clock tree synthesis (CTS) at nominal VDD and loading lower VDD libraries is more applicable than applying CTS directly in the sub-VT region. Mixing dierent VT transistors, also known as dual- VT method, has been employed customizing standard-cell buer for constructing robust clock networks. It has been approved in the simulation that this customized buer could increase the performance of delay, skew and slew by factor of 9.8, 8.9 and 9.8 respectively at 400mV.
Handledare: Babak Mohammadi (EIT) och Oskar Andersson (EIT)
Examinator: Joachim Rodrigues (EIT)