Godkända
Utvärdering och utveckling av hårdvaruanpassade approximations metoder för flexibel SPA baserad LDPC avkodare
Deepak Yadav (2015) och Afshin Seraj (2015)
Start
2016-12-05
Presentation
2017-09-22
Plats:
Avslutat:
2017-09-22
Examensrapport:
Sammanfattning
Signal Processing algorithms are usually developed using Matlab-code, C-code or other tools or programming languages. Before implementation of an algorithm in hardware description language, like VHDL or System Verilog, the algorithm must be converted from floating-point to fixed-point number representation. The fixed-point implementation involves balancing of performance loss compared to full precision operators, versus size of the fixed-point number representation. The fixed-point implementation can be in integer, floating-point of a defined number range or binary logarithmic format. For a given algorithm, different number representations result in different hardware cost, accuracy, and latency. Particularly, performing a multiplication/division in logarithmic system requires merely an adder in hardware, while performing an addition in this numeric system requires more logic, compare to floating point system. The wise choice of the hardware’s numeric system (which is highly algorithm-dependent) and operators, along with a proper trade-off between the cost, accuracy and latency, is an integral part of designing efficient arithmetic circuits.
Handledare: Liang Liu (EIT)
Examinator: Erik Larsson (EIT)