Laboratory Lessons
# Make sure you don't distribute any files located in below-mentioned paths
- DesignKit Files can be accessed from following path:
- /usr/local-eit/cad2/cmpstm/stm065v536/
Synthesis
- demo files generated after execution of following: inittde dicp19 or type
source /usr/local-eit/cad2/cmpstm/stm065v536/setup2018.efd
- Modelsim can be access using command: vsim
- To enable some extra debugging options in modelsim use command: vsim -debugDB
- Genus (Cadence synthesis tool) can be accessed by 'genus' command (To run the Genus in legacy_ui to access synthesis environment attributes type genus -legacy_ui)
- To show the graphical user interface (gui) use: gui_show
- If you end up being in common_ui environment (genus@root:>), type:
- ::legacy::set_attribute common_ui false /
- SRAM can be accessed locally from (SRAM size: 160 Words x 32bits per word)
- /usr/local-eit/cad2/cmpstm/mem2011/SPHD110420-48158@1.0
- All necessary files for synthesis & simulations (memwrapper, documentations ...) can be accessed locally from:Synthesis Lecture slides are available in /usr/local-eit/cad2/cmpstm/dicp18/Genus_Doc
- /usr/local-eit/cad2/cmpstm/dicp18
- For a better understanding of Technology files see this
- Remember NOT to include the behavorial file of the memory while performing synthesis (include only .lib files)
- Function model and stimuli file are here
- For back-annotation in ModelSim, see this
- If you have errors using the SDF file (e.g. negedge, posedge not found), try to use this Perl script and make sure you read the readme
Place and Route
- To be able to continue with next step you need a top module including the physical IO pads. Write your own top module with pads, and synthesize it with the tool to make a netlist including pads
- You should create an IO assignment file before being able to proceed further with PNR tool. see this to get an understanding what an IO assignment file is
- PADS are uploaded in dicp18 directory. See this for more information
- Place & Route Lecture slides here (a brief explanation on what exactly PNR does)
- PNR tool, encounter is available: (Using terminal go to your project dir, run initialization command and then 'encounter' )
- See this for Power/Ground pads connection to power rings
OBS:
- If you look for having modelsim simultor on your own laptop see this link for downloading student version
- Please look at the documentation to learn how to develop your design considering the memory: /usr/local-eit/cad2/cmpstm/mem2011/SPHD110420-48158@1.0/doc/C65LP_ST_SPHDL_BE/UserManual/C65LP_ST_SPHDL_BE.pdf
- A good practice is to write a testbench just for the memory (you have access to memory IO pins through the mem wrapper) to learn about its timing
- Remember, for modelsim simulation you need to compile the verilog model of memory (/usr/local-eit/cad2/cmpstm/mem2011/SPHD110420-48158@1.0/behaviour/verilog/SPHD110420.v) and for the synthesis and Place and Route you just need *.db, *.lib, *.lef depending on the tool