Laboratory Lessons
# Make sure you don't distribute any files located in below-mentioned paths
- DesignKit Files can be accessed from following path:
- /usr/local-eit/cad2/cmpstm/stm065v536
Synthesis
- demo files generated after execution of following: inittde dicp18
- Genus (Cadence synthesis tool) can be accessed by 'genus' command (To run the Genus in legacy_ui to access synthesis environment attributes type 'genus -legacy_ui')
- If you end up being in common_ui environment (genus@root:>), type:
- ::legacy::set_attribute common_ui false /
- SRAM can be accessed locally from (SRAM size: 160 Words x 32bits per word)
- /usr/local-eit/cad2/cmpstm/mem2011/SPHD110420-48158@1.0
- All necessary files for synthesis & simulations (memwrapper, documentations ...) can be accessed locally from:Synthesis Lecture slides are available in /usr/local-eit/cad2/cmpstm/dicp18/Genus_Doc
- /usr/local-eit/cad2/cmpstm/dicp18
- For a better understanding of Technology files see this
- Remember NOT to include the behavorial file of the memory while performing synthesis (include only .lib files)
- Function model and stimuli file are here
- Post- Synthesis Simulation: For back-annotation in ModelSim, see this
- If you have errors using the SDF file (e.g. negedge, posedge not found), try to use this Perl script and make sure you read the readme
Place and Route
- To be able to continue with next step you need a top module including the physical IO pads. Write your own top module with pads, and synthesize it with the tool to make a netlist including pads
- You should create an IO assignment file before being able to proceed further with PNR tool. see this to get an understanding what an IO assignment file is
- PADS are uploaded in dicp18 directory. See this for more information
- Place & Route Lecture slides here (a brief explanation on what exactly PNR does)
- Place & Route Guideline here
- PNR tool, encounter is available: (Using terminal go to your project dir, run initialization command and then 'encounter' )
- Make sure you read this and adapt the tool parameters and cells names in the guide above with 65nm
- See this for Power/Ground pads connection to power rings
Power Simulation
- Find the Power Simulation lecture slides here
- PT is a synopsys supported tool. Using PT, you need to use *.db files in target and link library native variable
- After running the PT tool, open the help, see the read_sdc command arguments and description. Some SDC commands are not supported in PrimeTime. Before being able to read your SDC file (output of pnr) correctly in the tool, make sure you remove or comment the unsupported lines and commands in SDC file.
- Make sure you create the vcd file by running post-layout simulation (sdf simulation using exported outputs from pnr tool)
- If you are getting any error during read_sdf, like Cannot find the instance, see this
- If you are getting any problem during read_vcd, like 0% coverage, see this
OBS:
- You can start learning the pnr flow and importing the design using these files. (it contains netlist,SDC and io assignment for a median filter sample design)
- Please look at the documentation to learn how to develop your design considering the memory: /usr/local-eit/cad2/cmpstm/mem2011/SPHD110420-48158@1.0/doc/C65LP_ST_SPHDL_BE/UserManual/C65LP_ST_SPHDL_BE.pdf
- A good practice is to write a testbench just for the memory (you have access to memory IO pins through the mem wrapper) to learn about its timing
- Remember, for modelsim simulation you need to compile the verilog model of memory (/usr/local-eit/cad2/cmpstm/mem2011/SPHD110420-48158@1.0/behaviour/verilog/SPHD110420.v) and for the synthesis and Place and Route you just need *.db, *.lib, *.lef depending on the tool