Approved
An Interface State Density Monitoring Circuit for Build-In Self-Test Applications
Viktor Sahlström (06)
Start
2012-03-08
Presentation
2012-06-08 10:00
Location:
Finished:
2013-01-15
Master's thesis:
Abstract
A Verilog-A model to be used when simulating interface state current effects on MOS-devices is developed. Furthermore a circuit measuring the same on chip is presented. The Verilog-A model together with a SPICE model is used to test and prove the functionality of the circuit. The result will be used to monitor the performance of circuits. The model uses an engineering approach and the feasibility is tested using simulations. The result of the project is a circuit able to measure interface state concentrations with an accuracy good enough to determine if a circuit with particular low interface state density requirements should be used or not.
Supervisor: Roland Temes (TU Berlin)
Examiner: Lars-Erik Wernersson (EIT)