Event
Thesis defense: 3D Integration Technology and Near-Memory Computing for Edge AI
Published: 2025-11-27
Arturo Prieto defends his thesis "3D Integration Technology and Near-Memory Computing for Edge AI".
Link to thesis in LU Research Portal.
Zoom link.
Zoom ID: 66847927874.
Higher performance through increased technology integration has focused on scaling transistor dimensions. However, the manufacturing process is increasingly expensive and faces technical challenges in the development of new breakthroughs. Evaluation of the third dimension has emerged as a promising alternative to scaling, which enables stacking of semiconductor components with 3D interconnections. Different technologies present different integration strategies, where 3D sequential integration (3DSI) enables small pitch for 3D contacts, allowing for high-integration circuits. A library of standard cells has been designed and characterized according to 3DSI, enhancing the high-integration capabilities of the technology for digital designs. This library compiles the required predefined logic cells that can be used in the design of a digital integrated circuit (IC).
The design of ICs as a foundation for edge AI is focused on enhancing memory and computing resources to improve the processing capabilities of such platforms. Computing architectures are traditionally based on the concept of von Neumann architecture, which distinguishes computing and memory units as two independent entities. However, near-memory computing (NMC) is presented as a viable alternative to the von Neumann architecture that brings computation closer to memory. NMC is non-intrusive to the conventional low-level structure of SRAM and enhances memory bandwidth for hardware acceleration. The integration of accelerators into resource-constrained platforms has been evaluated, expanding the functionality with custom hardware tailored for computation-intensive AI workloads. Furthermore, flexibility has been achieved by providing modularity to the design architecture.
The proposed architectures are evaluated by programs that highlight the performance of integrated AI hardware accelerators into edge devices, emphasizing the importance of software and hardware co-design. The contributions of this thesis focus on 3DSI technology circuit design and NMC architectures evaluating performance, energy and area efficiency.
| When: | 2025-12-12 09:15 to 2025-12-12 14:00 |
| Location: | E:1406 |
| Contact: | arturo.prieto@eit.lth.se |
Thesis defense: Near-Memory Computing Architectures for Scalable Edge AI Applications
Published: 2025-11-10
Masoud Nouripayam defends his thesis "Near-Memory Computing Architectures for Scalable Edge AI Applications."
Zoom link.
Zoom ID: 69455644174
Link to the thesis i LU Research Portal.
Artificial intelligence (AI) and machine learning (ML) are rapidly permeating nearly every aspect of modern life, from personal devices and autonomous systems to industrial automation and environmental monitoring. The growing demand for intelligence at the network edge is reshaping how computing hardware is conceived and built. Edge AI platforms are expected to deliver high throughput within tight energy and area budgets, operate reliably at low voltages, and adapt to diverse workloads, while data movement between processors and memory continues to dominate system cost. These trends position memory-centric computing as a compelling alternative to conventional architectures. By tightly coupling local memory, approximate processing, and near-memory execution, this work advances the development of compact, high-throughput, and energy-efficient AI hardware.
| When: | 2025-11-21 09:15 to 2025-11-21 13:00 |
| Location: | E:1406 |
| Contact: | masoud.nouripayam@eit.lth.se |
AI & Digitalization Breakfast Seminar: Certifiably Optimal Anisotropic Rotation Averaging
Published: 2025-09-29
When: Wednesday October 15, 2025 at 09:00-10:00
Where: Control Seminar Room M:3170-73
Register: for free breakfast at the seminar, register no later than October 10th by using this link.
Abstract: Rotation averaging is a key subproblem in structure from motion. Semidefinite programming relaxations are often used to solve the problem, and there are theoretical results analyzing difficulty and optimality. However, previous methos focus on the isotropic setting, where the intrinsic uncertainties in the measurements are not fully incorporated into the resulting optimization task. Recent empirical results suggest that moving to an anisotropic framework, where these uncertainties are explicitly included, can result in an improvement of solution quality. However, global optimization for rotation averaging has remained a challenge in this scenario. In this talk we show how anisotropic costs can be incorporated in rotation averaging. We also demonstrate how existing solvers, designed for isotropic situations, fail in the anisotropic setting. Finally, we propose a stronger relaxation and empirically show that it recovers global optima on a number of tested datasets.
Speaker bio: Carl Olsson is a Professor at the Computer Vision and Machine Learning division at Centre for Mathematical Sciences, Lund University. He obtained his PhD at Lund University in 2009, and has since then been in Lund and at Chalmers. His research addresses large scale optimization methods with applications in computer vision. A particular interest is in mapping and navigation problems such as structure from motion. His research aims at improving reliability of algorithms by developing methods that provide globally optimal inference, independent of initialization.
The Breakfast Seminar Series is sponsored by the LTH Profile Area AI & Digitalization.
| When: | 2025-10-15 09:00 to 2025-10-15 10:00 |
| Location: | Control Seminar Room M:3170-73, M-building, Ole Römers väg 1 |
| Contact: | susanna.lonnqvist@eit.lth.se |
Thesis defense: Ashkan Sheikhi
Published: 2025-09-04
Title of thesis: Scaling massive MIMO with imperfect transceivers.
Link to thesis in Lund University Research Portal
Zoom link.
Zoom ID: 67836255687.
The number of users and the information transmitted over wireless networks have been growing constantly during the last decades. Nowadays, the pace of this growth is extremely sharp because of the new applications which heavily rely on wireless networks to meet users' demands. Wireless networks infrastructures are constantly developing to meet these demands. Massive multiple-input multiple-output (MIMO) and large intelligent surface (LIS) are two of the main technologies which are the key-enablers for the current and future wireless networks. The performance gains achieved from these system are mainly due to the large number of deployed transceiver chains, which enables serving more users by exploiting spatial domain multiplexing to meet the higher service requirements. The possibility to scale up these systems is a necessity to constantly meet the network demands. Deploying massive MIMO and LIS systems with non-ideal hardware components is of great importance to make the scalability of these systems feasible. In theory, the performance of these systems can grow unboundedly by scaling up the number of transceiver chains. However, assuming ideal hardware components for the transceivers is not realistic from a practical point of view, since the number of transceiver chains are in the order of hundreds to thousands, and the deployment cost, processing complexity, and power consumption can limit the scaling of such systems.
This work presents an analysis of hardware quality, complexity, power consumption, versus performance of wireless communication systems, with a particular focus on massive MIMO and LIS architectures. We derive closed-form scaling laws that relate analogue front ends power consumption to key system and environmental parameters, such as bandwidth, signal-to-noise-plus-distortion-ratio (SNDR), and fading conditions, enabling informed decisions for low-power design. For massive MIMO systems, we explore both traditional and machine learning-based digital pre-distortion (DPD) strategies. In particular, we propose optimization of per-antenna DPD sizes under hardware constraints and adaptive neural DPD allocation strategies based on channel conditions, demonstrating substantial capacity improvements and system cost reductions. We further analyze the effects of non-ideal receiver chains on LIS, and propose efficient antenna and panel selection schemes to sustain LIS performance with fewer number of transceiver chains. Finally, we propose an over-the-air (OTA) method to jointly perform DPD and reciprocity calibration in massive MIMO and LIS systems, mitigating transmitter non-linearity and non-reciprocity without dedicated hardware or iterative algorithms. Collectively, these contributions provide new insights and tools for the design of energy- and cost-efficient wireless systems that remain robust under realistic hardware constraints.
| When: | 2025-09-19 09:15 to 2025-09-19 13:00 |
| Location: | LTH E-building, E:1406 |
| Contact: | ashkan.sheikhi@eit.lth.se |