Laborationer
The assignment can be downloaded here
- VHDL source files for synthesis lab: (demo files generated after inittde dicp13)
- Lecture slides for synthesis : download here.
- memories for synthesis : download here. Note RomCoeff.txt file has all coefficients set to zero, update the coefficients randomly.
- Example tcl script for synthesis : download here. memory.tcl has commands for linking memory files to dc.
- An example memory wrapper is provided here. Please note that the timing check should be set to false while doing behavioral simulations and switched on during synthesis !!!
- For post synthesis simulation use the attached verilog behavioral model.
- Placement files for the Place and Route laboration: download here.
- Lecture Slides for Place and Route lecture: download here.
- Reference manual for Soc Encounter: download here.
- Lecuter slides for extra Place and Route laboration: download here.
- Slides and example script for synthesis. For synthesis of memory check the memory.tcl script.
- Lecture Slides for PrimeTime lecture: download here.
- Files for the PrimeTime laboration: download here.
- Slide for FSMD: download here.
- Script for fixing SDF annotation for SoC Encounter (NOTE: details in README): download here.
Download the zipped files into a newly created directory and run the following commands to extract files
gunzip file_name.tar.gz
tar -xvf file_name.tar