Approved
Design of sub-threshold memory elements
Iman Mohajeri ()
Start
2009-12-01
Presentation
2011-01-31 11:15
Location:
E:2311
Finished:
2011-02-28
Master's thesis:
(Contact supervisor)
Abstract
In applications where power consumption is more critical than performance, Sub-threshold circuit approach is a very good choice. Efforts have been made to investigate characteristics of transistors in Sub-VT region to further decrease the power consumption. Since one crucial section of every synchronized digital system is register part, having high performance and reliable registers is a huge advantage. Moreover, some new areas are being introduced in recent years which put strict requirements on registers with speed and high reliability both together, among them are time domain ADC's. One the other hand,standard cell libraries are not optimized to work in Sub-threshold region, a customization is required to have much more efficient cells. The purpose of this work is to observe Flip-Flop architectures in Sub-threshold regime in 65 nm technology. First, characteristics and behavior of transistors in 65 nm technologies and with Sub-VT supply volt-ages is investigated. Then a few common architectures has been selected to be optimized for operation in Sub-VT. All architecture has been optimized and then compared considering power, delay,size and variability. At last the selected architecture has been changed and improved to give better performance. Based on selected architecture, a new configuration is introduced which shows better performance. Finally the layout of the new Flip-Flop has been drawn with the optimal size and a post-layout simulation is done to study effects of parasitic elements.
Supervisor: Syed Muhammad Yasser Sherazi (EIT)
Examiner: Joachim Rodrigues (EIT)