Approved
Novel Method of ASIC interface IP development using HLS
Chandranshu Mishra () and Anestis Athanasiadis ()
Start
2023-01-10
Presentation
2023-06-01
Location:
Finished:
2023-08-23
Master's thesis:
Abstract
Currently Ericsson is running several products with several different technologies (ASIC, FPGA, eASIC) and different vendors for which the digital front end is developed separately with vendor specific RTL generation tools. In particular, High Level Synthesis (HLS) is becoming an alternative description language allowing excellent final implementation results for certain specific IPs. These tools do particularly excel in generate filter chains quickly, allowing fast developing time. Having said that, not all possible coding style are best suited for an efficient implementation with some leading to worse results than other. Moreover, not all possible architectures for an IP lead to the most efficient mapping onto the actual HW. Finding the most versatile and most efficient architectures and coding styles are of paramount importance in today fast pacing Digital Circuits word where shortened Time-to-Market and constant cadence of product delivery are becoming imperative. Exploration seems the key for finding out the best solution that can adapt to different technology platform and vendor’s tool. In this Master thesis. We'd like to focus on some specific ASIC Interface IPs such as SPI, I3C.
Supervisor: Liang Liu (EIT)
Examiner: Erik Larsson (EIT)