Approved
An Embedded Logic Analyzer for Post-silicon Test and Debug
Philip Ljungkvist () and Jonas Johannesson ()
Start
2012-01-30
Presentation
2012-11-30 11:00
Location:
Finished:
2012-11-30
Master's thesis:
(Contact supervisor)
Abstract
Fabricating an Application Soporific Integrated Circuit (ASIC) is a complicated process with potential for errors. To know that the chip leaving the factory is working correctly, testing the chip is necessary. Testing can be done by applying data to the input and compare the output with data that is known to be correct. The test data at the input needs to be carefully chosen to be able to detect as many errors as possible. Modern ASICs can be built from several hundreds of million transistors. To design a system this complex a top down work flow is used. This enables the designer to describe the system on a behavioural level in a hardware description language and with help from software tools and hardware libraries translate the system into a physical transistor layout. Even if the fabrication of a chip was successful, errors caused by the designer might still exist. Finding where in a system an error is located is called debugging. To make debugging easier it is important to have a high observability of the system so that it is possible to know where in the design something is not behaving as anticipated. In a pad limited ASIC the minimum area requirement is given from the amount of input and output pads rather than from the area requirements of the core. Being able to test a system without having to use a high number of input and output pads can make the total area requirement of the system lower. In this master thesis a system is designed that is capable of testing and debugging a circuit using a small number of pads. This is achieved by using a serial connection between the chip and a FPGA based test controller. Because of the low speed of the serial connection, memories are used as buffers at the input and output of the tested system. The implemented system offers tools such as a triggering device and signal multi- plexers to make debugging of the system easier.
Supervisor: Joachim Rodrigues (EIT)
Examiner: Erik Larsson (EIT)