Approved
Using Approximate Computing Circuits to Optimize Power of an ASIC
Tien Hsing () and Padmashree Nuggehalli Srinivasa ()
Start
2022-10-04
Presentation
2023-06-13 09:15
Location:
E:2311
Finished:
2023-08-17
Master's thesis:
Abstract
With the ever-increasing demand for network cameras to support real-time image processing and machine learning applications, low-power solutions are needed. The advancement in technology scaling makes more complex computations on a single chip feasible, while it also becomes more challenging to optimize power. Although lowering the supply voltage is an effective technique for optimizing power, the physical limitations of CMOS technology make a further reduction of the supply voltage difficult. Hence, the focus is shifted to optimizing hardware circuits to reduce power dissipation. Regarding adders and multipliers being the basic operations in many image processing applications, some research has proposed to replace traditional accurate arithmetic circuits with simpler approximate circuits to significantly reduce energy consumption in the system. This approach provides a means of trading accuracy with power, performance, and area.
Supervisor: Liang Liu (EIT) and Mohammad Attari (EIT)
Examiner: Erik Larsson (EIT)