ETIN55 Integrerade A/D och D/A omvandlare
The lab assignments demonstrate some fundamental aspects of mixed mode simulations and modeling and they introduce CAD tools and simulators commonly used in research and development. The labs allow you to investigate different A/D converter architectures and some of their properties.
There are 3 assignments:
1. Modeling and studies of ADC fundamentals. (MATLAB) (20 hours)
2. Analog modeling with Verilog-A. (Cadence) (20 hours)
3. Modeling and simulation of a 5 bit flash ADC and an 8 bit pipelined ADC. (Cadence) (20 hours)
Notice that, to be allowed to work with Cadence, you have to confirm that you have read and accepted this Cadence NDA, by downloading, filling and signing this form, which you hand over to the course manager.
The assignments are rather extensive. The time required to solve them is approximately 60 hours. That means that the supervised hours (12) will not be enough and that work outside supervised hours will be inevitable! Be well prepared with preparations and questions at the supervised hours !!
Slides, manuals and simulation files:
All material you need for the three assignments can be downloaded from the Schedule page.
Requirements for pass degree:
PhD students work individually.
Undergraduate students work in groups of 2 persons.
In order to pass this lab course, each group of students shall hand in one lab report with simulation results, schematics and answers to questions given in the lab manual. The lab report must be one document, handed in in hardcopy.
DEADLINE!! One assignment report containing all three assignments shall be handed in by Friday 14 December at the latest.
The scheduled hours (12h) are supervised by Siyu Tan and Stefan Andric.