Forgot to sign up? There are spots available in this instance of the course. To do a late sign-up, contact your program planner! Refer her/him to this page in order to let them know that there are spots available. You do not have to contact the department beforehand, but you need to tell us your personal number so that you can be added to the labs. For program planners: There are available spots as long as this message is on the webpage!
If you want to re-register for the course this year, then send an email to Erik Göthe (email@example.com) with name, personal number, and course code.
The objective of the course is to describe structured methods for construction of digital systems, based on the concept of state transition graphs. The state transition graph is a powerful tool when building a model of the system. This model can then be realised by a sequential machine, which is a realisation with logic circuits and delay elements. It is central to the course to understand the concept of state transition graphs and how different methods can be applied in the realisation chain so the resulting circuit has few gates, which leads to a hardware with small chip area.
Course code: EITF65 (previously EIT020)
Credits: 9 hp
Activity terms: HT1 and HT2
Lecturers: Martin Hell (HT1), Andreas Johansson (HT2)
Examiner: Martin Hell
Course secretary: EIT's studentexpedition (Erik Göthe)
Students: Mandatory for D2 and E2; Optional for F2 and C3.
Examination: Written exam, laboratories
Kursombud 2019: Lina Elisabeth Tinnerberg (E), Elina Yrlid (E), Yuhui Tong (D), Fritjof Bengtsson (D)