Laborationer
The assignment can be downloaded here
- VHDL source files for synthesis lab: (demo files generated after inittde dicp14)
- Lecture slides for synthesis : download here.
- Synthesis resource : here - included scripts, mem models, mem wrapper etc. Also includes matlab script which generates random stimuli, should be used in the testbench.
- Remember to NOT include the behavorial VHDL files for the memories while performing synthesis (include only .db/.lib files).
- For back-annotation in ModelSim replace the vsim command in the do file with the command in this file (modify the paths and names of design).
- In case back-annotation errors occur, run this Perl script.
- General Guidlines for pushing your design through the flow (click me)
- Place and route lecture slides: here
- Place and route files: here
- Place and route guide: here
- If timing report cancels with problems related to AAE and OCV, try to type the following command in the terminal: setDelayCalMode -SIAware false
- Slides for power simulation can be found here (starting at slide 29)
- Changes for ST65 is found here.
gunzip file_name.tar.gz
tar -xvf file_name.tar