First page
Welcome to the digital track of IC Project 1.
The latest updates will be posted on this site.
20190527 The final presentations will take place in E:2311 at two different time slots.
2019-06-05 09:00 - 10:00
2019-06-07 09:00 - 10:00
You are only required to present once, please sign up groupwise here, and use this template.
Please submit your reports no later than June 10th.
20190515 If you are interested in various onlie course from Cadence, you should have a look here. This is compteley volunteerly.
20190502 The 2nd presentation by the individual groups is scheduled for May 13th. We start at 10:00 sharp in E:3139. A template for the presentation can be found here.
20190402 The 1st presentation by the individual groups is scheduled for April 8th. We start at 10:00 sharp in E:3139. A template for the presentation can be found here. For the GANTT chart you may have a look at this.
Project plan: ASIC design is an interative process, do not wait with the layout until the RTL is bug-free. Do the backend as soon as you now which resources (Memories, pads, etc) you need. The earlier the better for the project. Please rehearse the presentation before Wednesday.
20190327 The projects are assigned now, please check the table.
20190321 The projects are now uploaded. Please email me your #1 and #2 preference by Monday.
20190228 For the approval Masoud and I will be in the lab on Monday March 4th between 0830-1030.
The approval will take place as listed below.
- Demonstrate your final layout and simulations (could be a good idea if get some feedback from one of your course mates before)
- You need to explain individually you project
- You will be asked to do a miner change in your flow in we expect that you can implement this change by modifying the scripts.
20190210 Masoud and Julian will guide you through the physical placement on Friday 15th between 08-12 in the lab and in E:2311. Ideally you can use your already synthesized netlist of the matrix multiplier. Please be aware that you do not have to have a bug-free code for place and route. The main objective is setting up a script for the entire flow. This task can be veyr time-consuming the 1st time. Please come peroared by looking att the slides and try to start the tool.
20190204 On Friday February 8th at 10:00 we will meet in the lab to support you on remaining issues with the synthesis flow. By Friday you should have an almost complete synthesis script in place. You do not need to have bug free RTL for a synthesis, the flow can be implemented independently.
20190128 On Monday February 4th at 0815, Masoud will go through the ASIC synthesis flow, which will be very different from what you have learned for FPGA synthesis.
During the synthesis session you will take a dummy design through synthesis, and by the end of the session you are expected to have your own flow.
This flow will be the reference for matrix multiplier, which means you only have to change a few parameters to adjust it to the matrix multiplier.
20190122 The compulsory assigment is available under projects
20190115 Welcome to the Introduction meeting on Monday Jan 21th at 10:15 in E:2517. This meeting is for all.