First page
Course code: EITF20 Credits: 7.5 Activity term: HT2,
Lectures: 10 x 2 hours; First lecture Tuesday 2017-10-31 (13.15-15.00) E:B Laborations: 4 x 4 hours; First lab Tuesday 2015-11-15 8-12 E4118/19 |
Course environment, and dependencies:
:
Course related questions:
How can Gene Amdahl help you decide which enhancement is the best?
Is a larger cache better than higher clock frequency?
What is a superscalar CPU?
What is the difference between a direct mapped cache and a set associative?
How come a TLB is essential to virtual memory efficiency?
What is pipelining?
Is out-of-order execution really possible?
How can the hardware rearrange your program?
Why is pipelinng faster than combinatorics?
Different levels of caches - why?
Snooping on busses?
Is the ARM ISA a RISC?
How much memory bandwidth does a modern CPU need?
How to ensure cache coherence in a multi-core system?