VINNOVA Industrial Excellence Center - System Design on Silicon
2008-01-01 -> 2017-12-31
High frequency electronics
High frequency electronics is of critical importance to wireless devices, like mobile phones, and thus to the companies involved. With high performing electronics, the quality of service can be high also in severe radio conditions, where the received signal is very weak and strong interference is present. The high frequency electronics is also important since it consumes a significant part of the power budget, and savings can result in significantly increased battery time. To companies in consumer electronics it is essential that the cost in mass production is low. Thus, we focus on design of circuits in CMOS technology. As the supply voltage drops in scaled CMOS technology, the use of passive mixers for frequency conversion becomes more important. Our research on low voltage RF circuits and passive mixers already started ten years ago, resulting in patent applications from Ericsson on both a topology for quadrature passive mixers, and a linearized passive mixer using bootstrapping. As passive mixers are used in current state-of-the-art mobile phone receivers, we currently investigate how their second-order non-linearity can be improved, resulting in yet another patent filed by Ericsson. This is under development within the EU FP7 Dragon project, with technical coordination Ericsson. Along the trend of low voltage we also investigate ultra low power circuits for wireless communication, where the speed of modern CMOS is used to allow even radio frequency circuits to operate at ultra low current, under the so called threshold voltage. Applications for this kind of circuits are found for instance in medical implants like pacemakers and hearing aids. The high frequency performance increases as CMOS technology is scaled to ever smaller feature sizes. It is therefore today possible to use CMOS technology in microwave and millimeter wave applications. Among current industrial applications at this frequency, microwave links are probably the best example. An industrial PhD student (now graduated) from Ericsson in Mölndal has been active in the project. Mölndal is the Ericsson site developing microwave links for the backhaul of cellular base-stations. In the Medea+ project Hi-Mission, lead by Ericsson, we demonstrated the microwave capabilities of CMOS combined with low loss carrier technology passive components in a system-on-package solution. We also have an active research on beamforming transceivers, where several new concepts have been demonstrated in silicon, including the latest, a two-channel fully integrated beamforming receiver with analog baseband phase rotation. Last year we received the APMC Prize for our PLL based beamforming architecture. Our very latest result, not yet published, represents a break-through in millimeter wave power amplifier efficiency, with more than 20dB gain and a measured power added efficiency of 37% at 60GHz.
Reduction of the number of filters is of key interest to the companies in the center. The antenna interface, often referred to as the front-end, is situated between the antenna and the high frequency electronics. It consists of discrete passive components like filters, duplexers, and switches. These components are both bulky and expensive, and with the increasing number of radio frequency bands in mobile phones, each band requiring a set of discrete acoustic wave filters, the cost of the radio becomes dominated by the antenna interface. This must be approached in several ways. One is to make the receivers more linear and transmitters less noisy. Another is to try to make filters and duplexers that are capable of operation in several bands. A duplexer is a device containing filters to allow a receiver and a transmitter to simultaneously use an antenna at different frequencies, so called frequency division duplex (FDD). Our team cooperates with Prof. Faulkner, Victoria University, on cancellation based active duplexers. Another important issue for the companies is that to cover multiple frequency bands the antenna must either be large, but that is not accepted in today’s small phones, or the performance will suffer. By using adaptive impedance matching, providing near optimum antenna impedance to the high frequency electronics regardless of the actual antenna mismatch, some performance can be retrieved. We started this research early with an industrial PhD student (now successfully graduated) from Perlos in CCCD. Significant performance improvements were demonstrated for DVB-H receivers with CMOS based solutions. There is currently a strong interest in industry for adaptive matching, and this year we have had two masters’ theses this, one at Sony Ericsson and one at ST-Ericsson, so probably this will soon reach products. We currently have two projects addressing this topic, one on circuits investigating transmitters with adaptive matching, and one lead by the radio systems group investigating MIMO system performance increase with adaptive matching. To handle the strong transmitter signals we will start using MEMS technology, in combination with CMOS.
Frequency synthesis is one of the key functions in all kind of radio designs. The personnel in SoS has a long-standing tradition in voltage-controlled-oscillator (VCO) design, with some best-in-class published results. Even in this case the involvement of Ericsson and ST-Ericsson is deep and committed, sometimes resulting in designs that find their way directly into products (e.g. the VCO recently presented at ESSCIRC). Yet another area of intense activity is the design of digital phase-locked loops (DPLL), which have become immensely popular in recent years, after the seminal efforts of Texas Instruments. While definitely not a magical block, a DPLL is much more digital-friendly than the analog PLL (APLL), and as such is the most promising PLL architecture fro designs in nm CMOS processes. SoS is hosting a post-doc fellow (funded at present through a VR grant) who has already a very good experience in DPLL design and who is currently designing a new DPLL based on an improved time-to-digital converter (TDC, the key block replacing the traditional charge-pump in APLLs). In this work we have availed ourselves of a fruitful collaboration with a researcher from the University of Pavia, Italy, who has repeatedly visited us thanks to several grants from “Telefonaktiebolaget LM Ericssons stiftelse för främjande av elektroteknisk forskning”. DPLL have not yet found their way in products delivered by ST-Ericsson in Lund, but it is a fact that other groups in ST-Ericsson are planning to employ DPLLs in the near future, and it is important to acquire such an industrial competence in Lund as well.
The importance of this function, bridging the analog and the digital world, is second to none – even in the most aggressive software-radio design the A/D converters will be needed to convert the unavoidably analog signal from the antenna. Also in the field of A/D converters the collaboration between SoS and industry has been ongoing for several years, providing the added value to the research projects. The most relevant result for both academia and industry has been a Delta-Sigma converter designed by a former SoS PhD student under the supervision of an Ericsson researcher. This converter is now part of the latest radio release from ST-Ericsson, which is no mean feat for a PhD work. Furthermore, this research has resulted in an outstanding scientific output, with papers published at a top conference (ESSCIRC) and in world-leading journals (IEEE JSSC and IEEE TCAS). This line of research is now continuing with a new PhD student (also funded EU FP7 Dragon project) co-supervised by two Ericsson IC designers, one being the former PhD student. In this way the otherwise problematic transmission of knowledge to the next PhD generation occurs in a straightforward way. As can be expected, the new A/D project is highly relevant to Ericsson and ST-Ericsson, addressing the specifications of LTE Advanced (release 10) in a very timely fashion, which guarantees for both the scientific novelty of the work as well as the strategic relevance for the industrial partners of SoS.
The digital baseband processing has in the last 20 years evolved for a one-band GSM phone into a mobile terminal with numerous frequency bands and standards. Today, baseband processing is experiencing challenges like concurrent support of multiple standards, which in turn creates a demand for highly efficient data processing, on platforms that offer flexibility and scalability. Furthermore, new algorithms and concepts like multiple antenna systems are constantly being introduced into the wireless terminal with an ever increasing demand for higher calculation capacity. At the same time power consumption should not increase. Therefore, research on efficient baseband architectures are of crucial interest to keep the competitiveness of the industrial partners. Consequently, the focus within the digital ASIC group is on subjects closely related multi-mode baseband processing with special emphasis on low-power applications. The industry partners confirm a strong interest in the conducted research projects by offering their expertise as well as facilities. The research has a long tradition in investigating new concepts within baseband processing and finding novel hardware architectures to reduce the power consumption. Hardware architectures for key digital baseband modules are developed and investigated for their power efficiency and the impact on system performance, e.g. reduced wordlength effects on system performance. Examples of such blocks are encoding/decoding, synchronization, channel estimation, and modulation and results are published at key conferences and journals (e.g. TCAS-I & II, TVLSI, JSAC). Examples of concepts that early on was investigated at the university are OFDM (Orthogonal Frequency-Division Multiplexing), now the dominant modulation technique in evolving wireless standards, and multiple antenna techniques, e.g. Multiple-Input Multiple-Output (MIMO). MIMO has been introduced for wireless systems, e.g. in Long Term Evolution (LTE and LTE-A). Systems based on MIMO and OFDM are becoming extremely complex for the digital baseband processing. The requirements for higher data rates are continuously increasing and escalating power consumption follows. The research on baseband circuitry for OFDM started in the early 90’s and multiple antenna systems around 10 years later, before the techniques were mature for commercial systems. During the last decade the group has involved in several EU projects, i.e. Pacwoman, Magnet, Magnet Beyond, and Multibase. The group is the leading academic group on designing digital baseband circuitry in Sweden.
Today, the evolution of wireless communication standards continuously drives the development of underlying computational platforms with increased complexity demands. Additionally, the requirements on time-to-market and non-recurring engineering (NRE) cost force today’s hardware platforms to be updatable to adopt succeeding amendments of the standards. Thereby, doing re-spins on dedicated hardware accelerators for each of the standard updates is not affordablewith regard to both time and cost. Furthermore, future user terminals are expected to support more than one single radio access technology, capable of efficiently switching between different networks, in order to obtain a continuous connection or constant data rate transmission. Hence, flexibility has become one of the essential design parameters to allow computational platforms to cope withvarious standards and to support multiple tasks concurrently, coarse-grained reconfigurable architectures (CGRA) are being considered as an alternative to ASICs, FPGAs and DSPs. Through previous projects an architecture for an CGRA was developed and this effort is continuing within SoS. The CGRA has been adopted into the EU FP7 Multibase project as part of a Digital Front-End handling the coarse grain synchronization unit for multi-standard OFDM, e.g. LTE, DVB-H and WLAN IEEE802.11n, in close cooperation with Ericsson. In addition, FFT processing has been investigated as a crucial part of any OFDM system. A key obstacle is the lack of mapping tools for algorithms onto such architectures. Therefore, a cooperation has been initiated with the embedded systems project of the sister center EASE to investigate those problems. In addition, reconfigurable computing is part of the ELLIIT strategic initiative, see section 9. One of the former PhD students, Henrik Svensson, is currently at Ericsson in Kista and is cooperating with the SoS project.
Low Power Digital Techniques
In current CMOS technologies, static power reduction has become a major design constraint, in industry as well as in academie. Enormous design efforts are required to keep the static power at a minimum, which poses a demand on scalable architectures which are suitable for multi-supply voltage ASICS with retention mode, i.e., certain power domains will be disconnected from the power supply when not active. However, these techniques have an overhead due to hardware that facilitates retention mode, i.e. power controller, retention register, etc. Moreover, verification on RTL level becomes cumbersome since the runtimes of CAD tools are extremely long, and verification on FPGA is only possible to a certain extent. Therefore, we carry out research on architectures which offer flexibility at a high scalability. Furthermore, we see a high potential in voltage scaling, where the main drawback, i.e. speed degradation, needs to be combated by architectural optimization techniques. Performance modeling at a scaled supply voltage is constrained by the offered functionality of commercially available CAD tools and the models provided by the ASIC vendors. The digital ASIC group is able to refer to a novel simulation model that characterizes design on netlist level. The model offers design space exploration relatively early in the design flow, at a negligible short run-time with only limited reduction in accuracy. We believe that above mentioned techniques, has has and will continue to have a huge impact in industry. Another design strategy we are focusing on is sub-threshold design which is applicable for application with low to moderate throughput requirements, e.g. wireless networks incorporating medical implantable devices with extreme power budgets (BANs). Here, were evaluating power reduction techniques for their effectiveness in the weak inversion region. We see that equal design effort needs to be spent on dynamic/static power reduction and throughput improvement. Sub-threshold design has gained in popularity in academia and we believe that a lot of companies, in a first phase for instance in biomedical engineering, will benefit from our findings. Furthermore, we see that wireless communication is continuously moving into new fields and that the importance in biomedical engineering is increasing.
With the scaling of the transistor technologies beyond 20 nm gate length, it is harder to maintain electrostatic control in the transistor channel and major efforts are undertaken to continue the transistor scaling. Among the candidates of emerging technologies are Si nanowires and III-V MOSFETs. Lund University has a unique position in this field due to early initiatives in the areas of nanotechnology and device implementation in the form of scaled III-V nanowire MOSFETs. The activities related to emerging technologies within the SoS VINNOVA Industrial Center act as a bridge between the basic research efforts, primarily funded by other programs, and the more industrial research effort within this program. For instance, the competence within the SoS center has been used to identify test vehicles for the emerging technology development at Lund University. Basic radio circuits (LNAs and mixers) are currently being implemented in III-V nanowire transistor technology under the SSF program “Wireless with wires”. While the circuits act as a drive for the technology, they also allow an early evaluation of the technology potential.