Godkända
Custom-cell Design for Sub-Vt Memories
Babak Mohammadi ()
Start
2011-03-12
Presentation
2012-01-13 13:00
Plats:
Avslutat:
2012-04-26
Examensrapport:
Sammanfattning
Supply voltage scaling is a very popular technique to reduce energy dissipation, and leads to near-threshold or even subthreshold circuit operation when applied aggressively. Digital designs may be conveniently synthesized with commercially available standard-cell libraries which unfortunately are not optimized for scaled voltages. Moreover hard macros like RAM may not work at all at aggressively scaled supply voltages. Therefore, it is desirable to a small custom designed standard- cell library allowing for the automated synthesis of memories. In this project, various leakage minimization techniques like transistor stacking, transistor channel stretching, and hardware minimization are evaluated. The target technology is 65 nm CMOS.
Handledare: Oskar Andersson (EIT) och Syed Muhammad Yasser Sherazi (EIT)
Examinator: Joachim Rodrigues (EIT)