Godkända
Komponentdesign för digitala satellitmottagare
Nadir Muhammad Khan (2008)
Start
2010-02-15
Presentation
2010-07-15
Plats:
Avslutat:
2010-10-05
Examensrapport:
(Kontakta handledare)
Sammanfattning
Aim of this thesis is design and implementation of high speed, resource efficient components for digital satellite receiver. Components which are designed during this thesis work are Automatic Gain Control, Pre Filter, Digital Down-Converter, Decimation Filter and Matched Filter. Receiver components are designed for a multi-carrier oversampled signal of 140 MHz bandwidth. Advanced pipelining and parallelization is used to make receiver capable of handling 140 mega samples/sec. Filters are implemented using a combination of both direct and time shared architectures to achieve speed and reduce resource consumption at the same time. The thesis explains each component in detail. First functionality is discussed, and then issues which are hurdles in the way of implementation and their solutions are discussed. Then hardware architectures of block and sub-blocks with their symbol and port details are presented. Synthesis results, maximum clock frequency and verification of components individually and in the form of chain are presented at the end.
Handledare: Marco Krondorf (Techniche Universitat Dresden)
Examinator: Peter Nilsson (EIT)