Godkända
Tekniker för att förbättra prestanda och tillförlitlighet för integrerade minnen med låg matningsspänning
Hamed Movahedimeimandi (2017)
Start
2019-04-05
Presentation
2019-09-05
Plats:
Avslutat:
2019-09-23
Examensrapport:
Sammanfattning
Most of the area and power budget of today’s SoCs are consumed by memory. Among different kinds of memories, SRAMs thanks to their higher power efficiency, are ideal for electronic devices specially Internet of Things (IoT) appliances. With spreading of IoT appliances more struggles have been done to improve SRAM main features such as power consumption and silicon area. Power consumption directly translates to the battery life of the device, while silicon area is an important factor in the total cost of the IoT device. One popular method to reduce the associated power consumption with memories is to lower the supply voltage. As long as the expected performance is met, this method provides a significant power saving in memories. On the down side, the reliability of memory operation is also affected. That means significant increment in the chance of a failure during read or write (R/W) operation. One cause of the failure is the bitcell itself. Memory bitcells are designed to work under nominal voltage in a certain technology node. However, in reduced voltage conditions their reserved state might unwantedly change during a simple read operation. In the same way, during writing to some target bitcells, the state of other bitcells might unwantedly change. To maintain the functional reliability of the memories in reduced voltage conditions some sort of Read /Write (R/W) assist techniques are commonly used. One popular technique is to boost voltages of only the desired nodes via the help of some kind of R/W assist circuitry. Another source of failure in memory operation is Sense Amplifier (SA) since it is a module that takes the decision on a state of a bitcell to be either 0 or 1 during a read operation. The reliability of SAs decrease when the supply voltage is reduced. In fact, most of the time the SA itself could be the bottleneck in reducing the memory operational voltage even further. This thesis deals with the reliability issues that arise when memories are designed to operate in low voltage conditions. For that matter, an available low voltage memory architecture is studied first. Then, voltage boosting circuit solutions are considered. The required circuit experiments and simulations are pursued to reach to a reasonable and helpful solution. Unlike some previous works, the aim here is to propose a solution that has the least silicon area overhead. Effort on maintaining SRAM functional reliability continues with analysis and study around SA circuitry. The aim here is to suggest a circuit or approach that is most suitable for SRAM memories operating in lower than nominal supply voltage condition. Circuit simulations, analysis and evaluations would be provided to accompany the proposed or studied techniques during the thesis work.
Handledare: Babak Mohammadi (Xenergic) och Henrik Sjöland (EIT)
Examinator: Pietro Andreani (EIT)