Godkända
Digital Correction of DAC mismatch in continuous time Delta-Sigma AD Converters
Siyu Tan () och Yun Miao ()
Start
2013-10-28
Presentation
2014-06-27 10:15
Plats:
E:3139
Avslutat:
2014-10-08
Examensrapport:
Sammanfattning
The popularity of the continuous time A/D converter has increased dramatically in recent years. A major limitation in resolution in such a structure is unit element component mismatches during chip fabrication in the rst feedback DAC. Such mismatches cause the DAC to become non-linear, which degrade the signal to noise ratio of the whole modulator. In this work, a 4-bit, third order, single-loop, continuous-time converter with digital background correction of component mismatch in the rst DAC has been designed, simulated and fabricated in a 65nm CMOS process. The modulator is clocked at 144 MHz with an oversampling ratio of only 8. The mismatches found in the rst feedback DAC is digitally estimated based on cross-correlation and correction can be done using derived correction factors thereafter. In the analog modulator, low-power loop lter with excess loop delay compensation is implemented. The feedback loop is formed by resistive current mode DAC. The SNDR is 67.5dB within 9MHz bandwidth. The digital correction runs in background.
Handledare: Mattias Andersson (EIT) och Pietro Andreani (EIT)
Examinator: Joachim Rodrigues (EIT)