Godkända
Analog Adaptive Equalizer for a Clock-Less System
Vinoth Kannan (2010)
Start
2011-11-01
Presentation
2012-06-05 13:15
Plats:
E:2311
Avslutat:
2012-06-15
Examensrapport:
(Kontakta handledare)
Sammanfattning
This thesis implements a slope detection based analog adaptive equalizer in 140nm CMOS technology for a USB 3.0 redriver application. This thesis is performed in the Mixed Signals Solutions group at NXP semiconductors, Eindhoven, The Netherlands. Due to the scaling of IC technology, the speed and performance of integrated circuits is continuously increasing. Designing a chip operating at Multi-Gbps becomes a feasible solution. However, the bandwidth of the interconnect scales at a much lower rate compared to the on-chip bandwidth, thus making the communication link between chips the major bottleneck for the overall system performance. Signal crosstalk between the adjacent lines becomes more significant, when transferring large volume of high-speed data over a parallel transmission lines. So the high speed communication interfaces are moving from parallel data transmission to serial data transmission to reduce the crosstalk issues. Serial interfaces also have the advantage of lower pin counts, thinner cables and smaller connectors leading to significant cost reduction. USB 3.0 is a serial interface standard that specifies a maximum transmission speed of upto 5Gbps in each direction, which is ten times faster than USB 2.0 (480Mbits/s). The main drawback at this high speed data transmission is the loss of signal integrity over longer cable lengths or PCB traces. Also, a USB 3.0 host or device can be connected to cables of different length. A Redriver IC plays a vital role in maintaining signal integrity over a lossy transmission line. The Redriver IC is analog in nature and does not perform clock and data recovery. The main purpose of the redriver IC is to restore the signal quality of a deteriorated input signal. Equalizer is one of the key component inside the redriver IC. Implementing an equalizer with fixed gain setting will result in non-optimum ISI at receiver input. Therefore, an adaptive equalizer to automatically detect and compensate the channel loss is preferred. This thesis focuses on implementing a slope detection based analog adaptive equalizer for such a redriver application. Analog implementation of adaptive equalizer has the advantage of lower power consumption compared to digital implementation. The implemented slope detector architecture does not perform the clock recovery. The adaptive equalizer is modeled in Verilog-A, along with the characteristics of microstrip channel, USB 3m cable and the adaptive loop operation and convergence behavior are simulated. The transistor level implementation of adaptive block and limiting amplifier consumes 11.7mW of power from a 1.8V supply. The performance of the adaptive block is simulated with difference process corners and it shows excellent results.
Handledare: Markus Törmänen (EIT)
Examinator: Henrik Sjöland (EIT)