Godkända
Hardware Implementation of a LTE Channel Estimator
Chaiwat Sittisombut ()
Start
2009-08-01
Presentation
2010-04-16 10:15
Plats:
Avslutat:
2010-04-29
Examensrapport:
(Kontakta handledare)
Sammanfattning
In Long Term Revolution (LTE), a pilot-assisted channel estimation can be implemented by sending reference signal or pilot is along with data signal. The transmitting signal between transmitter and receiver can be distorted by noise and fading in multipath. An accuracy of the transmitted signal through channel at the receiver requires channel estimation technique to acquire channel knowledge. In this thesis, various LTE channel estimation techniques are investigated. Their performance in terms of Bit Error Rate (BER) and Mean Square Error (MSE) are considered, and the trade-offs between performance and hardware complexity are investigated. The robust MMSE sliding window channel estimation technique is simulated in floating-point arithmetic to find an optimal number of pilots per window. Through fixedpoint simulations, it was found that a 8-bit word-length is optimal to represent the robust MMSE sliding window with 20 pilots per window. A hardware implementation of a 8-bit estimator was implemented with unfolded multipliers that uses in Blahut’s complex number multiplier in order to reduce the computational complexity. A Matrix multiplier was implemented by multiply and accumulate technique to achieve hardware reusable. The hardware was verified using post-synthesis simulations. However, this thesis is not designed for the entire LTE receiver chain. Thus, some important module such as Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) or equalizer is not implemented. The hardware architecture of the LTE estimator was mapped into both 130 and 65 nm CMOS technologies. In 130 nm CMOS technology, the estimator requires 0.308 mm2 chip area and consumes 0.927 mW of power. In 65 nm CMOS technology, the chip are and total power consumption are 0.159 mm2 and 0.795 mW, respectively. The maximum achievable throughput and maximum clock frequency in both technologies are 200 Mbps and 207 MHz, respectively.
Handledare: Farzad Foroughi (EIT)
Examinator: Joachim Rodrigues (EIT)