Godkända
Customization of Ibex RISC-V Processor Core
Rahul Raveendran () och Subhajit Bhuinya ()
Start
2020-12-02
Presentation
2021-06-14
Plats:
Zoom
Avslutat:
2021-06-28
Examensrapport:
Sammanfattning
The main objective of this thesis is to customize a CPU core known as Ibex based on an open source ISA known as RISC-V so that when it is implemented in a system for specific application it gives us desired performance. Another objective would be to reduce the processor gate count for a limited number of activity detection based radar algorithms. In order to customize the CPU core first we run the reference algorithms on Ibex core and evaluate the results. Based on evaluation of the result parameters like performance(speed), area, device utilization, the customized Ibex core architecture must be implemented for radar activity detection applications.
Handledare: Liang Liu (EIT) och Mohammad Attari (EIT)
Examinator: Erik Larsson (EIT)