Godkända
HLS för effektiv design och verifikation
John Johansson (2016) och Alfred Johansson (2016)
Start
2019-09-02
Presentation
2020-01-22
Plats:
Avslutat:
2020-02-21
Examensrapport:
Sammanfattning
Hardware design and development is a costly undertaking, not only because hardware is expensive to manufacture but because of the hours of developing, designing, debugging and testing. Because of the latter there has been a push towards HLS development in languages such as system-C which aim is to do hardware design on a higher, more modular level. Lately the companies that delivers these design environments has gained some traction on this push and this thesis aims to evaluate the efficiency and performance of one of these, Xilinx HLS development platform Vivado HLS. Ericsson has expressed an interest in the new HLS-tools because of their potential to increase the abstraction level during design of components and test environments. The increased abstraction levels could reduce the time it takes to develop and design hardware, which is the motivation behind this thesis. This thesis will cover an evaluation of Xilinx Vivado HLS tool, which will be a part of a larger project at Ericsson where they look to evaluate HLS tools from different tool developers. This document will summarize the project background, its aims, goals and the methodology of how to meet those goals. It will also briefly cover the potential challenges and results that can be expected during this thesis.
Handledare: Liang Liu (EIT)
Examinator: Erik Larsson (EIT)