Första sida
A doodle for an information meeting will be mailed during the 1st week of the study period.
For the verification part you are expected to synthesis you design from IC-Project I on a FPGA.
For some designs it could be necessary that you need to scale down the implementation.
After succesful post-layput simulation you need to use the Logic Analyzer to capture the data on the FPGA output.
Alternatively, are we offering measurements on ASICs that were fabricated in one of our research projects.