Första sida
Welcome to Introduction to Structured VLSI Design
2016-07-26 Please have a look at the course syllabus and course schedule.
2016-07-26 First lecture, August 29, Monday, 13.15-15.00, Room E:1147/1149.
2016-08-29 Please sign up for Labs as a team here.
2016-09-02 The Lab group and the sequence for Lab 1 can be found here. Please finish the Lab 1 assignment before the Lab and cross check beteween groups (e.g., SVD01 and SVD02 check each other)
2016-09-04 Our Lab starts next Wednesday. Will try to fix the Lab access and computer log in by then. Please make sure that you have a valid LTH ID.
2016-09-09 Next Monday (2016-09-12), Rakesh will talk about storage elements in Xilinx FPGA and give Vivado tutorial on IP generator and Integrated Logic Analyzer.
2016-09-12 An Example project with memories and ILA is now available
2016-09-14 No lecture next Monday (2016-09-19)
2016-09-29 No lecture next Monday (2016-10-03)
2016-09-29 Invited lecture from Ericsson next Tuesday and the slide is avaliable here (2016-10-04)
2016-10-05 Next Monday (2016-10-10), we continue the discussion with Ericsson, I also would like to wrap up the course content, Rakesh will present Lab 4&5.
2016-10-10 Here is a link to the suvey for our Ericsson guest lecture. Please be active and give feedback.
2016-10-17 There will be limited TA support (not the whole 4 hour slot) in the labs for this week during the standard hours, Wednesday and Thursday (13-17). If TA is not present please write an email to Steffen!
2016-10-17
Note:
- Lab 1,2,3 approval in Friday morning (8-12)
- Lab 4,5 approval in Friday afternoon (13-17)