Första sida
For the verification part you are expected to synthesis you design from IC-Project I on a FPGA.
For some designs it could be necessary that you need to scale down the implementation.
After succesful post-layput simulation you need to use the Logic Analyzer to capture the data on the FPGA output.
The login for the computers on the 4th floor are
2icp01
to
2icp08
passwd: 15Change.
Please use one account per group only and change the password.