Laborationer
The laboratory manuals will be placed here continously
Read the lab manual and solve the preparation problems before the lab.
The assignment in Lab 1 needs to get aproved by the TA no later than Sep. 25.
The information in this lab will be used in Lab2 and Lab3. Note your results carefully and try to learn different functions of tools you are using in this lab.
Lab 2 (Lab 2 manual updated to version 1.0.2 to correct some text issues)
Note: Deadline for lab 2 and 3 extended by 1 week. Final deadline to get approved in the labs Oct. 17.
ADDITIONAL Assignments!
These projects are for those who want get a grade better than 4!
Note: The highest grade in the exam will be 4. This assigmnet will only be considered to upgrade to grade 5. It is not possible to upgarde from not passing to grade 3.
Other benefits doing these projects?
- You will have a better understanding of transistor level design procedure
- You will learn more about the tools and their functions
- You can use your and your classmates' designs later in IC-Project course
Projects:
A full design of some selected gates. Design should include schematic, symbol, layout and full characteristics like power and timing analysis. Layout MUST be in standard-cell format which means that it should follow some additional design rules to be compatible with other commercial cells. If you are interested for any of these designs contact Babak. You can even come up with your own custom gate if it has at least 14 transistors, and TA agrees.
- Mirror adder
- Master slave positive edge triggered register using multiplexers
- ...