Laboratory Lessons
If the door to the lab room 4121 is closed you can open the lab room 4118 which has a card reader and go from there to 4121.
Make sure you change your password when you log in the first time!
A few slides on Questasim are here.
A simple example on how to implement a 1-bit adder on FPGA is available here.
Tutorials on Xilinx ISE can be found in S:\Tutorials\
The sequence will be distributed by Steffen during the second lecture. You need to sign up for the lab in order to get a sequence.
Assignment 1: Sequence Detector, Deadline Sept. 13 Test files Sequence
Assignment 2: KeyBoard Controller, Deadline Sept. 27 Provided files (VHDL Code, Presentation)
For Assignement2, please note that the testbench is not perfect and is just a reference !! (for e.g. the keyboard clock is clocked 4 times faster than system clock instead of 1000.)
Assignment 3: ALU, Deadline Oct. 4, Provided files (VHDL Code, Presentation)
Assignment 4: A calculator with memory and a display with VGA controller. Deadline Oct. 18th.
UPDATED MANUAL WITH SOME ADDITIONAL INFO
Assignment 5: Implemetation of a square root unit and an integrated system. Deadline Oct. 30th.