Kursprogram
Lectures
Mondays 10-12 in MA05 and Thursdays 8-10 in MA06
Schedule:
- Mon 2013-10-28 MA05: Performance, Quantitative principles; HP Ch. 1 (slides)
- Thur 2013-10-31 MA06: Instruction set architectures, ISA; HP Ch. 1.3, App. B (slides); Article: , "GPU vs. CPU Computing"
- Mon 2013-11-04 MA05: Pipelining I; HP App. A.1-A.5 (slides)
- Thur 2013-11-07 MA06: Pipelining II; HP App. A.6-A.7, Ch. 2.1-2.6, 2.9 (slides)
- Mon 2013-11-11 MA05: Pipelining III; HP Ch. 2.4-2.8,3.1-3.4 (slides) (Pipeline Summary)
- Thur 2013-11-14 MA06: Memory systems, cache I; HP Ch 5.1, 5.3, (App. C.1-C.3) (slides)
- Mon 2013-11-18 MA05: Memory systems, cache II; HP Ch. 5.2, (App C.2-C.3) (slides)
- Thur 2013-11-21 MA06: Memory systems, virtual memory; HP App C.4, Ch. 5.5-5.6 (slides)
- Mon 2013-11-25 MA05: Storage Systems, I/O; HP Ch. 6.1-6.4, 6.6-6.7 (slides)
- Mon 2013-12-02 MA05: Case studies, Special purpose processors, embedded; HP App. D
(slides);
Questions - Mon 2013-12-09 MA05: On demand - Cache, course summary, exercises
Question hours (frågetimmar)
- Tues 2013-12-10, 10-12 in E:4115 (lab-room)
- Thurs 2013-12-12, 8-10 in E:3139
- Fri 2013-12-13, 10-12 in E:4115 (lab-room)
- Tues 2013-12-17 10-12 in E:3139
Laboratories
There are 4 laboratories
You need to sign up for the labs via the 'Sign up' page in the menu to the left! (Rooms E:4115, E:4116)
- (Week 46) Pipelined processors.
- (Week 47) Advanced pipelining.
- (Week 48) Cache memory.
- (Week 49) Advanced cache, tradeoffs.
Assessment
Examination through approved labs followed by a successful written examination