First page
Welcome to the digital track of IC Project 1.
The latest updates will be posted on this site.
20170605 The final student presentation is scheduled for Friday 20170609 at 13:00 in E:2311 lab will be he template for the presentation here. The last day to submit your report is June 19th.
20170511 The lab will be occupied by another course. The dates where the lab is not available between 13:00-17:00 is
May 11th, May 12th, May 15th, May 19th, May 22nd
Pads: Please use foolwing pads for you design, the libraries can be found here /usr/local-eit/cad2/cmpstm/joajox
component CPAD_S_74x50u_IN --input PAD
port (
COREIO : out std_logic;
PADIO : in std_logic);
end component;
component CPAD_S_74x50u_OUT --output PAD
port (
COREIO : in std_logic;
PADIO : out std_logic);
end component;
20170504 The 3rd student presentation is scheduled for Thursday May 18th at 11:00 (sharp) in E:2311.
20170502 The 2nd student presentation is scheduled for Thursday May 4th at 11:00 (sharp) in E:3139. The template for the presentation is here
20170427 The doodle for the 2nd student presentation is here.
2017030 The 1st student presentation is scheduled for Monday April 3rd at 10:00 (sharp) in E:2517. The template for the presentation is here
20170327 The doodle for the 1st student presentation is here.
20170317 Good luck with your exam today. We will be in the lab today from14:00 to present the projects.
- You are expected to be able to discuss in detail both the RTL implementation and the design flow.
- You need to demonstrate that you have a clean script for synthesis and PnR.
- You will be asked to do small modifications in the RTL/ design flow
- Your overall Architecture
- the ASMD (according to Chapter 11 in "RTL Hardware Design Using VHDL", VLSI course book"
- A caption to every figure and that you refer in the text to the caption, and explain what is demonstrated. A figure is always an aid that makes a story comprehensive.
- Modelsim waveforms where you guide the reader on how to see that everything works fine. Please use decimal notational, use black white only and inverse the colours.
- Identify the critical path
- How did timing and area change for setting different constraints during synthesis.
- Cross check the number of multipliers and FFs you have been inferring in the RTL and what the synthesis tool produced. This need to be documented in your report.
- Screen dump of the final layout
- Compare the critical path after synthesis to after PnR
- Highlight any improvements/design optimisations
20170130 A TA will be in the lab on Wednesdays between 10-12.
20170125 The date for two coming sessions were decided today:
Synthesis: Mo January 30th 0830
Place and Route: Mo February 13th 0900
20170115 The assignment is uploaded now. A TA will be available on Wednesday Jan 25th at 10 in the lab
20170115 An information meeting is scheduled for Wednesday at 09:00 in E:2311. This meeting is for the analog and the digital track.