Faraday Technology Corporation
From the nice people at this company we have gotten a design kit for the UMC 0.13um process.
It contains two digital libraries (high speed and low leakage) with standard cells and io-pads.
A memory compiler and some PLL stuff are also available.
Use of, and access to, this kit is restricted to those belonging to the CCCD group.
The procedure for synthesis, place-and-route, and final touch with the layout editor described
below is intended for the 8metal version of the process. The older pages describing the six
metal version can be found here.
Synthesis
The synthesis is now prepared for the Synopsys 2004.06 version. The following command willmake the definitions and copy some setup files.
> source ~synopsys/v2004.06/far_setup
The setup files contain links to the available libraries, which are
fsc0h_d_sc : High Speed, Standard Cells All libs has a _tc , _bc , and _wc
fsc0h_d_io : High Speed, IO Cells version. Changes are made in the
fsc0l_d_sc : Low Leakage , Standard Cells local .synopsys_* files as usual.
fsc0l_d_io : Low Leakage, IO Cells
Some manuals can be found in $FAR_LIB/hdoc/ and /ldoc/ .
It is not possible to add IO-pads to the design within the Design Analyzer. There are two ways
to circumvent this. The pads can be added to the resulting verilog-file or they can be specified
in the vhdl code before synthesis. Use the core-limited pads, i.e. the ones that end with a B.
The other pads will not work well in Encounter without some modification to the library files.
Memory Compiler
The Faraday memory compiler (v200410.2.1) for the fusion process will be made available bythe synthesis startup script, far_setup. The main gui is then started by the command 'memaker'.
This version is able to create all sorts of output, including layout.
Some documentation can be found in the directory $FTC/doc .
Newer Memory Compiler
A more modern version (v200601.1.1) of the memory compiler can be accessed by running thefar_setup2 script instead. In this version the Two Port Register File is usable. The rest remain
unchanged.
Simulation
Simulation are performed in the ModelSim v6.0 tool. Simulation
can be executed before or aftersynthesis. Use the command
> source ~mentor/msim6.0a/setup
to define the environment. The file modelsim.ini, copied in the process, will contain references to
the correct libraries. It might need editing to get rid of unwanted libraries.
Simulation with NC Verilog
For those who want to try and simulate with the Cadence tool NC Verilog, it is initiaized along withthe analog stuff, see UMC 0.13um .
Place'n'Route
The place-and-route of the construction is now performed by the new Cadence tool Encounter.It should be better at handling the smaller dimensions of the Faraday process than the older Sili-
con Ensemble.
The tool can be used after the usual initialization , 'source ~umc/umc_setup8', of the environment.
It is then started with the command 'encounter'. Do not use an ampersand (&) here. The window
from which Encounter is started will serve as the command input window.
A small tutorial from Cadence is available. It contains directions on how to download the database,
which every user has to do by themselves since it involves a registration procedure and a signing of
a non-disclosure-agreement. Replace the copy command on page 3 in the tutorial with this one
'cp -r $SOCDIR/share/fe/gift/tutorials/dtmf/* .'
The command '$FAR_LIB/build_socdir8h' will copy some setup- and command files that executes
an example design in Encounter. The entire place-and-route session is launched by the command
'source MedFilt.com' from the command window. Naturally the commands are also available from
the tool menues.
When the design is ready, it has to be moved into the layout editor (dfII) for final fixing up, bond-
pads have to be added. The pads used does not contain any bonding area. DRC checks must also be
executed. The transfer of the design is done by exporting a stream file, which describes the entire
design, from Encounter. Invoke the command Design > Save > GDS and fill in the names of the
stream file to be created and of the mapfile, faraday_soc.map.
When this is done, start up Cadence dfII as described below and import the stream file.
Cadence Layout
When the design has been routed to satisfaction, it is still not ready for fabrication. The pads do notcontain the bonding-area, only logic and buffers, so this has to be added. For the moment it is only
possible to do in the layout editor Virtuoso in the Cadence Design Framework (dfii).
Thus, the design has to be transferred into the dfii environment. This is done by generating a stream-
file in Encounter before it is shut down, see the median filter example for the command.
The dfii environment then has to be initialized. This is done by the same setup-script that defines the
Encounter milieu. Look above! The program is started with 'icfb'.
Importing a Stream File from SOC Encounter
Follow this procedure to import the design, as a stream-file, from Encounter.* Copy the Layer map-file, $UMC_DIR/stream.map .
* Create a Cadence library, to hold the design, and attach it to the 'umc13mmrf' technology.
* Execute the command 'File > Import > Stream'. Fill in Input File and the name of the newly
created library. In the User-Defined Data form, enter the name of the Layer map-file and in
the Options window, select Retain Reference Library and enter 'FSC0H_IO8 FSC0H_SC'
at Reference Library Order. If the Low-Leakage cells has been used, use the library names
'FSC0L_IO8 FSC0L_SC' instead.
The design should now exist in the desired library and can be further dealt with as described below.
Adding Bonding Area
There is a conversion library (XPAD) for some of the pads in the high speed and low leakage libra-ries. This contain a bonding-area connected to the pad. To use this, select the pad and change library
reference to 'XPAD' and add on a '_C' to the cellname, i.e. change XFMHB to XFMHB_C.
For other pads and libraries the procedure below can be used. Also move the origin of the design to
the lower left corner.
The bonding area to be used is called PAD8MH and can be
found in the library FSC0H_IO8 .
Place it, like in the figure, on the outside of an IOpad and fill
the space between the cells with metal to make a connection
from the pad to the bonding area.
Note that the origins of the cells are facing each other which
will make it easy to place the bonding area a fix distance from
the IOpad.
Recommended distance are 5um from the IOpad and a spacing
of at least 4um between the bonding areas.
Design Rule Check
- The setup script for df2 will also set up the environment for some Design Rule Check (drc) by the tool
- Assura. To run, click on Assura > Run DRC in the layout editor window. Make sure that the cell to be
- tested are the one chosen in the popup form. Run Directory is where Assura will write temporary and
- log files during checking. This can grow awfully big and might have to be moved into some temporary
- area with enough free space. Click on Apply to start.