Joachim Rodrigues, Associate Professor
My current research focuses on power minimization techniques for digital ASICs. In my current project I am working on sub-threshold standard-cell based circuits in 65 nm CMOS. Energy dissipation in these circuits is minimized by architectural optimization. Several designs were already fabricated and measuremnts prove that the circuits are fully operational down to 250 mV. The project is funded by Vetenskapsrådet.
Chip photograph of a 65 nm sub-VT Asic. Layout of a mult-project die [1mm2] in 65 nm.
May 2009 [VLSI-SOC 2009] December 2009