Thesis defence: III-V Devices for Emerging Electronic Applications
Today?s digitalized society relies on the advancement of silicon (Si) Complementary Metal Oxide Semiconductor (CMOS) technology, but the limitations of down-scaling and the rapidly increasing demand for added functionality that is not easily achieved in Si, have pushed efforts to monolithically 3D-integrate III-V devices above the Si-CMOS technology. In addition, the demand for increased computational power and handling of vast amounts of data is rapidly increasing. This has led to an increased interest in quantum computing, offering the potential to solve specific complex problems more efficiently than conventional computers. Superconducting transmon Quantum Bits (qubits) are promising for the realization of quantum computers, which has led to an increased interest in cryogenic electronics. For these applications, III-Vs are suitable as their high carrier mobility enables low power consumption, low noise, and highly transparent superconductor-semiconductor interfaces. High-quality interfaces between superconductors and semiconductors are crucial for the implementation of gate-tunable hybrid superconductor-semiconductor qubits known as gatemon qubits.
This thesis explores the potential of utilizing indium arsenide (InAs) and indium gallium arsenide (InGaAs) nanowire and quantum well devices in these emerging electronic applications. Both as an add-on in Si-CMOS technology, as well as the channel material in electronic devices for cryogenic applications.
The electron transport in near surface quantum wells is studied by DC-measurements in combination with applied magnetic fields, from room temperature down to cryogenic temperatures. Several different ways to extract the carrier mobility are investigated, such as standard current-voltage sweeps, the Geometrical Magnetoresistance Effect (gMR), as well as the Hall effect. A deeper understanding of electron transport at cryogenic temperatures is obtained by the development of a model for the current characteristics of long-channel InGaAs quantum well Metal-Oxide Semiconductor Field-Effect Transistors (MOSFETs), which includes the effects of band tail states, electron concentration-dependent mobility, and interface trap density. The model shows an increased effect of remote impurity scattering associated with mobility degradation in the subthreshold region.
A demultiplexer based on an InGaAs nanowire network was fabricated, to enable routing of DC-currents on-chip and reduce the number of connections to the cryostat. To facilitate system-level investigation of circuits containing Josephson Field-Effect Transistors (JoFETs), a compact model was developed which by circuit simulations accurately reproduced the measured data from our JoFET.
Finally, a process for the growth of InAs nanowires on tungsten was developed. This novel approach is based on Template-Assisted Selective Epitaxy (TASE) and allows for easy 3D-integration of III-V devices in Si-CMOS technology.
Link to thesis i LU Research Portal:
|2024-02-23 09:15 to 2024-02-23 13:00
Thesis defence: Vertical III-V Nanowire Tunnel Field-Effect Transistors: A Circuit Perspective
The energy scaling of integrated circuits has reached its limit because the operating voltage of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFET) based switches has reached its minimum value. MOSFETs are limited by thermionic emission and cannot achieve a subthreshold swing (SS) below 60 mV/decade at room temperature. Tunnel Field-Effect Transistors (TFET), which operate on field modulation of band-to-band tunneling (BTBT), can deliver SS less than 60 mV/dec and are considered as a potential alternative for MOSFETs to further scale down the supply voltage.
This thesis work studied the capabilities and limitations of n-type TFETs based on III-V vertical nanowires and their circuit implementation. TFETs were fabricated using vertical InAs/GaSb or InAs/InGaAsSb/GaSb nanowires of high material
quality, and, switching from InAs/GaSb to InAs/InGaAsSb/GaSb allowed for optimization of the heterojunction, resulted in improvement of the device metrics. Along with heterostructure optimization, the dopant introduction and concentration were systematically varied to achieve devices with record performance. These devices achieved a minimum subthreshold swing of 42 mV/dec and a record high I60 of 1.2 ?A/?m at a drive voltage of 0.5 V. The stability and high yield of the process allowed for statistical study of correlations between important device parameters such as I60, on-current, subthreshold swing, and off-current. The implementation of circuits was also aided by sufficient process repeatability and yield.
To implement circuits based on these TFETs, the fabrication process was optimized with introduction of mesa and nonorganic spacers. Voltage based circuits in the following configurations were implemented: a current mirror, a diode connected inverter and a cascode buffer. Individual TFETs in the circuit operate well below 60 mV/dec operation with minimum achieved subthreshold swing (SS) of 30 mV/dec at drain voltage of 400 mV. In circuit operation, individual devices were connected via FEOL and are biased at 300 mV supply voltage, with an input frequency of 200 kHz. To explore current-mode based design principle, a current conveyor circuit was implemented, which exhibits large-signal voltage gain of 0.89 mV/mV, a current gain of 1 nA/nA and an operating frequency of 320 kHz.
Additionally, self-heating in a vertical nanowire device was examined using pulsed IV methodology. The results indicate that the intrinsic temperature rises to 385 K when the device is operated in DC at room temperature (300 K) with a thermal time constant of 1 ?s. We find that self-heating is a limiting factor for device performance.
Link to thesis i LU Research Portal:
|2023-12-15 09:15 to 2023-12-15 13:00
Thesis defence: Taming Cloud Integrated Systems in the Wild
This thesis unfolds a journey into the realm of cloud integrated systems. More specifically, it explores the transformational role of diverse cloud infrastructure, be it public or private, centralized or edge-based, when integrated into traditional systems. In this transformation, the cloud assumes the vital role of controllers. Inevitably, this shift towards cloud integration also brings into play the expansive network that acts as the connective tissue between traditional systems and the cloud, adding another layer of complexity to the newly formed integrated system.
In this work, we shed light on the less-talked-about side of cloud integration. Beyond the evident benefits of this transition, we face an array of challenges that emerge along with the introduction of the cloud and its accompanying network. Adapting traditional system deployment to this new era of cloud-based computing is one such necessity. The advent of virtualization and container technologies introduces additional requirements for software management. Shared infrastructure mandates stricter control over incoming traffic. Furthermore, real-world networks often act unpredictably, straying from their simulated behaviours. Even the much-touted 5G technology has not completely lived up to the expectations set a decade ago.
However, the ambition of this thesis does not lie in the enhancement of existing infrastructure, the improvement of cloud technologies, or the acceleration of network speed. Rather, it aims to accept and work within the limitations and flaws inherent in both cloud and network infrastructures. The primary goal is to recognize the chal- lenges these systems introduce, embrace their imperfections, and adapt our systems to work effectively with the realities of our imperfect cloud and unpredictable network environments.
To accomplish this, the thesis undertake a comprehensive analysis of two types of cloud integrated systems?Cloud RAN and Cloud Control System. A central focus is the evaluation of the practicality of implementing these systems using existing infrastructure. This evaluation is based on rigorous simulation as well as hands-on testbed experiments. In response to the insights gained from these assessments, the thesis proposes an innovative framework, built on a microservice architecture, to de- ploy cloud services more effectively for these systems. This framework is designed to mitigate the network latency impact brought on by unpredictable, ?wild? environments. It does so by incorporating specialized prediction and estimation services, thereby enhancing the adaptability of these systems to real-world challenges.
|2023-12-08 09:15 to 2023-12-08 13:00
|Lecture Hall E:1406, building E, Ole Römers väg 3
PhD thesis defence: Iman Ghotbi
This thesis primarily focuses on the design and implementation of a low-voltage, low-power RFFE tailored for direct sampling receivers in 5G FR1 applications. The RFFE consists of a balun low-noise amplifier (LNA), a Q-enhanced filter, and a programmable gain amplifier (PGA). The balun-LNA employs noise cancellation, current reuse, and gm boosting for wideband gain and input impedance matching. Leveraging FD-SOI technology allows for programmable gain and linearity via body biasing. The LNA's operational state ranges between high-performance and high-tolerance modes, which are apt for sensitivity and blocking tests, respectively. The Q-enhanced filter adopts noise-cancelling, current-reuse, and programmable Gm-cells to realize a fourth-order response using two resonators. The fourth-order filter response is achieved by subtracting the individual response of these resonators. Compared to cascaded and magnetically coupled fourth-order filters, this technique maintains the large dynamic range of second-order resonators. Fabricated in 22-nm FD-SOI technology, the RFFE achieves 1%-40% fractional bandwidth (FBW) adjustability from 1.7 GHz to 6.4 GHz, 4.6 dB noise figure (NF) and an OOB third-order intermodulation intercept point (IIP3) of 22 dBm. Furthermore, concerning the implementation uncertainties and potential variations of temperature and supply voltage, design margins have been considered and a hybrid calibration scheme is introduced. A combination of on-chip and off-chip calibration based on noise response is employed to effectively adjust the quality factors, Gm-cells, and resonance frequencies, ensuring desired bandpass response. To optimize and accelerate the calibration process, a reinforcement learning (RL) agent is used.
Link to thesis in LUCRIS:
|2023-11-24 09:15 to 2023-11-24 13:00