Godkända
A Low Energy Data Compression Sub-Vt ASIC for Brain Implants
Longyang Lin () och Shuai Cheng ()
Start
2012-12-20
Presentation
2013-10-10
Plats:
Avslutat:
2014-01-06
Examensrapport:
Sammanfattning
In this report, a digital implementation of a data compressor for wireless brain machine interface with an attractive area and low energy cost is presented. This design consists of pre-processing lters, spike detectors, a spike compressor and the Serial Peripheral Interface (SPI) IO protocol, targeting the 65 nm CMOS technology. Area and energy dissipation have been dramatically reduced by resources sharing, architectural optimizations and using a standard-cell based latch memory. Moreover, the compression ratio for each channel is adjustable based on the channel quality and the requirement of spike reconstruction accuracy. The loss of the reconstruction accuracy of the xed-point digital implementation is less than 0.1% compares to the full precision Matlab model. Additionally aggressive voltage scaling (down to the sub-VT region), clock gating and multiple clock domains have been performed resulting in a total die area of 900500 m2 for 16 channels. Energy dissipation in the sub-VT region is estimated using a high-level sub- VT energy model. The estimated value is 1.03 pJ/clock cycle, which is 30 improvement compared to the standard super-VT implementation without clock gating.
Handledare: Oskar Andersson (EIT) och Palmi Thor Thorbergsson (EIT)
Examinator: Joachim Rodrigues (EIT)