umc130b.html

UMC 130nm Design Kit

This is the full design kit for the United Microelectronics 130nm process.

There is a digital cell library from Faraday Technology available. It consists of standard
logic gates and IO-pads in a high speed and low leakage version.

[ The older digital library OldFaraday is still available. ]
[ So is the older version of this page. ]

The environment can be initialized and started by the commands

> source ~umc/umc_setup
> icfb &

As usual this will also copy some setup files and a previously empty directory should be used.
New (Cadence)libraries should be attached to the 'umc13mm' technology for the standard ver-
sion of the process. For RFCMOS design, use 'umc13mmrf' instead. They should not be mixed.
Although it might work at fabrication it will not be possible to run lvs and extraction on such
a design.

There is a lot of ducumentation, start with these (someone out there loves long filenames)

$UMC_DIR/doc/

GT-DBT-030806-001_Ver.2.2.pdf                                                                                                              # Kit Manual
G-02-MIXED_MODE_RFCMOS13-1.2V_3.3V-1P8M-MMC_FSG_L130E-EDR.PDF                       # Proc. Params
G-03BE-GENERATION13-TLR_BEOL.pdf                                                                                                # BEOL Design Rules
G-03-LOGIC13-1.2V_3.3V-1P8M-HS-TLR.pdf                                                                                     # Older BEOL Rules
G-03-MIXED_MODE_RFCMOS13-1.2V_3.3V-1P8M-MMC_L130E-TLR.PDF                                 # More Rules
G-1B-077.PDF                                                                                                                                                # Metal Rules
G-04-MIXED_MODE_RFCMOS13-1P8M-MMC_FSG-INTERCAP.pdf                                             # Cap. Values
G-05-MIXED_MODE_RFCMOS13-1.2V_3.3V-TWIN_WELL_MMC_L130E-SPICE.PDF                # Sim. Info
G-05-MIXED_MODE_RFCMOS13-1.2V_3.3V-TWIN_WELL_MMC_NOISE_L130E-SPICE.PDF    # Noise
G-06-MIXED_MODE_RFCMOS13-1.2V_3.3V-1P8M-MMC_L130E-MASKTOOL.PDF                  # Mask Info

$UMC_DIR/TwinWellModels/*.pdf        # More documentation of the models.

More info on the rf-models can be found in the document

$UMC_DIR/MM_RF/models/Rf/L130E_RFCMOS_model_v1.1p1.pdf

Design Checks

For design verification the Cadence Assura tool is used. If there is a menu-header labeled Assura
in the layout editor, the tool is avaiable. If not, help should be required.

Design Rule Check

Select Assura > Run DRC in the layout window. Then choose Technology umc013 in the window
that pops up. Also set Rule Set to either standard or rfcmos depending on the design. A number
of runtime Switches can also be set. Click on View RSF to get a list of the available switches.

Select a Run Directory where the data- and log-files can be stored by the Run Name. Remember
that big designs implies big data sets.

When all is filled out, hit Apply !

The errors will then be presented in an easy-to-use browser.

Now, there is also possible to check for antenna errors. Use the Rule Set Antenna.

Quick LVS guide

Pins in the layout view has to be created as text labels ( Create > Label ) in the same layer as the
structure on which it is put. Make sure it is completely enclosed by the wire or rectangle.

When LVS is started ( Assura > Run LVS ) a form will pop up. Make sure that the settings for the
schematic and layout source are correct. Select Technology and Rule Set as above and click Apply.

Parasitic Extraction

Only after a successful lvs run can the parasitc components be extracted from the layout. Select
Assura > Run RCX to activate the form. Make sure that Technology and Rule Set are set correctly.
Set Output to Extracted View to create a new cellview (av_extracted) containing the reslut of the
extraction. Under the flap Extraction select Cap Extraction Mode to Coupled and type in 'gnd!'
at Ref Node. Click on Apply and wait for it to finish.

If all works well the cellview av_extracted will now contain the result of the extraction. This can
be used in a post-layout simulation together with the hierarchy editor as usual.

Always finish with the Assura > Close Run command to shut down Assura in a proper way.

LVS and RCX problems

There are still some problems with the various components when running lvs and extraction. At
least these works in the process. Some gives wrong result in lvs but works in post-layout simulation.

RFCMOS Don't use !

P/N_12_RF MIMCAPS_MML130E
MIMCAPS_RF P/N_12_HSL130E
RNHR_RF P/N_LV_12_HSL130E
RNPPO_RF (wrong in lvs) P/N_HGLV_33_L130E
L_SQSK_RF P/N_HG_33_L130E
L_CR20K_RF (wrong in lvs)
MOMCAPS_VP1_RF, MOMCAPS_VP2_RF

Standard Don't use !

P/N_12_MML130E MIMCAPS_MML130E
RNND_MML130E
NCAP_MML130

When using inductors; make the connection with the same layer as the connection point, from
outside the CAD117:WY layer enclosing the component.

Mixed-Mode Simulation ( and LVS )

The standard cell library ( High Speed ) may now be used for mixed-mode simulation. Major
changes have been made to the setup-files '.cdsinit' and '.simrc' . Delete these before running
the setup-script and the new ones will be copied.

Use the symbols from the FAR07_HSC or FAR07_HIO standard cell libraries together with
the transistor symbols from the umc13mmrf library in the schematic design.

Create a config view of the testbench as usual and use this one to select how each cell should be
simulated. The view symbol means that the digital simulator will be used.

Start the 'Analog Environment' and set the simulator to spectreVerilog. At 'Simulation >
Options > Digital' make sure that Options File is set to
'/usr/local-tde/cad3/far07/syn2007/verilog.opt'.

The default Interface Elements used are set for 1.2 Volts.

Mixed Mode LVS has not been tested yet!!!