STMicroelectronics CMOS028 SOI v2.9

Digital Design Flow

The libraries in this design kit contain standard cells and can be used for design synthesis and functional verification with a set of design tools available.

Synopsys Design Compiler v2015 : Design Synthesis

Synopsys PrimeTime v2015

Mentor Graphics QuestaSim v10 : VHDL and Verilog Simulation

The tools are briefly described below. There are also exstensive manual sets within the tools.

For information about the process itself look at the instructions for the analog editor.

Note:

Only available on the secret cluster of machines - markov, motala, popov. Special account required.

Encounter stuff not ready yet!

Setup

All the tools needed are initialized by one command which should be run in an empty subdirectory the first time. A lot of setup and example files will be created if they do not already exist.

> source /usr/hidden/cmp/soi28v25/digsetup

The setup routine will create a file structure similar to this one.

StartDir
___________________________|______________________________
| | | | |
vhdl netlists WORK work soc

Use StartDir as default location when running Synopsysor ModelSim. The Encounter tool, when
ready, must be started from the library soc. The function of the other directories are

vhdl : folder for vhdl-files.
netlists : output files from synthesis
work & WORK : storage libraries for ModelSim and Synopsys.

Synthesis with Synopsys

The standard cell libraries have been prepared for use with Synopsysand ModelSim as described in the example design.

C28SOI_SC_12_CORE_LL : Standard Cells, Low Vt.
C28SOI_SC_12_CORE_LR : Standard Cells, Regular Vt.

If others are to be used changes have to be performed in the setup file .synopsys_dc.setup as usual.
There are an extensive set of different lib files for various conditions to choose among.

The synthesis program is started by the command design_vision .

The small example is started by the command 'source comp.dv' .

Simulation

Simulation is performed in the QuestaSim tool, which can handle both vhdl and verilog files. Simulation can be executed before or after synthesis. The simulator tool is started by the command 'vsim'.

There is a small example command file that runs through an entire simulation. This is executed by typing 'vsim -do medfilt.cmd' at the shell prompt.

There is a lot of documentation available from the tool menues. Also a lot of pdf-documents in the library $MODEL_SIM/docs/pdfdocs/ or by checking $MODEL_SIM/docs/index.html .

Place and Route

To be done