STMicroelectronics 28nm CMOS SOI v2.9
This new version of the design kit is required for new designs. The process has
been modified. Some of the changes are
- The metal layes B1 and B2 no longer exists.
- No MIM capacitors available.
-
As usual it is only available on the secret cluster of machines - "marconi",
"popov", and "motala".
In time this design kit can also be used by the
digital tools for synthesis with the tools from
Synopsys.
The
old version 2.5f will not be used anymore.
Notes
- We have no longer any home-made pad library that works.
-
Setup procedure
The environment is defined by a setup script which is called by the command
>
source /usr/hidden/cmp/soi28v29/setup
The first time this is run, the script will also copy some files that are necessary for proper
operation of the design kit. Afterwards the
Cadence design tool can be started by
> virtuoso &
Connect new libraries to technology
cmos32lp.
To access the home made pad library add the following to the
cds.lib file
DEFINE LU_PADS_8M /usr/hidden/cmp/LU_PADS_8M
Using Momentum
If the use of the
Momentum tool from
Keysight is required
use the script
setup.mom instead.
Remove the file
.cdsinit the first time so that a new one can be copied.
There are plenty of documentation for
ADS and
Momentum in the directory
/usr/local-eit/cad2/keysight/ADS2017U1PDF/.
Documentation
There is also an extensive set of maunuals which can be read by the web browser by the command
>
firefox -no-remote $PDKITROOT/doc/html/index.html
Simulation
Use
Launch > ADE L to start the Simulation environment.
Make sure that your local
'corners.scs' file is filled in at
Model File,
(
Setup > Model Libraries), .
Design Rule Check
Make sure it reads
$U2DK_CALIBRE_DRC_DECK at
Rules.
For
Antenna checks use
$U2DK_CALIBRE_ANTENNA_DRC_DECK instead.
Here is a file listing some
errors
that are acceptable since they will be fixed by tiling etc.
LVS
For
LVS, make sure it reads
'$PDKITROOT/DATA/LVS/CALIBRE/LVS_std' in the
Rule File box. Do not forget to tell
LVS to export the schematic netlist.
Parasitic Extraction
In order to extract the parasitic components in the design a procedure that uses both
Calibre and
Cadence QRC is used. It is shortly described in the first part of
the file
$PDKITROOT/DATA/PEX/QRC/README .
This is how it goes.
Use Calibre to create a database, svdb.
Copy the file
$PDKITROOT/DATA/PEX/QRC/calibreqrc.ctrl to your working directory.
Replace "myCell" with your own cellname. The layout and schematic are probably named
something like this
LAYOUT PATH "lvsRunDir/cellname.calibre.db"
SOURCE PATH "lvsRunDir/cellname.src.net"
Execute with
calibre -hier -lvs calibreqrc.ctrl >& lvs_qrc.log
Use Calibre to convert the previously created database.
Copy the file
$PDKITROOT/DATA/PEX/QRC/calibreQRC.query.ctrl. Also create a new library,
AGF.
There are several places where "myCell" have to be changed. Afterwards run
calibre -query svdb < calibreQRC.query.ctrl >& calibre_ci.log
Time for extraction with Cadence QRC.
For help with
QRC run
$QRC_HOME/tools/bin/cdnshelp.
Start by copying
$PDKITROOT/DATA/PEX/QRC/qrc.ccl.
Here are a lot to change. At the beginning the
extraction type is set ( rc_coupled, c_only_coupled...).
At the end, set the
extraction corner (FuncCmax, FuncCmin, FuncRCmax, FuncRCmin, nominal).
Uncomment the section that deals with
LVS to
QRC flow. Make sure that cellnames and
libraries are set correctly.
Uncomment the section that generates the extracted view.
Now it is time to execute
qrc -cmd qrc.ccl >& qrc.log
There should now be an
av_extracted view of the cell in your library.
Slightly More Automatic Extraction
There is a primitive script that generates the command files and executes the three steps above.
Please test it by typing
$ST28SOI/xtract MyCell MyLib Ectraction_Type
MyCell : Cell Name
Mylib : Library Name
Extraction_type : Type of Extraction Required, f.i. "c_only_coupled"
As usual anything can go wrong!
Tiling
For the tiling step follow the procedure described in the file
$PDKITROOT/DATA/SMART_TILING/CALIBRE/README
The required variables are already set.
> calibre -gui -drc -runset $MGC_CALIBRE_SMART_TILING_RUNSET_FILE
The layout can be generated or picked from earlier drc runs.
Put the name of the design at
Top Cell.
This will generate two stream files;
<cell>_TILES.BE and
<cell>_TILES.FE which can be read into a new library and instanciated in the design.