Electrical and Information Technology

Faculty of Engineering LTH | Lund University

CV

Mattias Borg, Associate Professor

Details

Born in Malmö, Sweden, December 3rd 1982. Married since 2008, one child.

Experience

May 2016 – Now, Lund Institute of Technology, Assistant Professor

Department of Electronic and Information Technology

 

March 2016 – April 2016, Lund Institute of Technology, Researcher

Department of Electronic and Information Technology                

June 2014-February 2016, IBM Research - Zurich, Research Staff Member.

Leading development of CMOS-compatible III-V device integration on Si using template-assisted selective epitaxy (TASE). Responsible for III-V MOVPE system, and IBM responsible for two EU projects (INSIGHT, NanoTandem). Heavily involved in EU project E2Switch on TFETs.

 

May 2012-May 2014, IBM Research - Zurich, Post-doctoral researcher.

Responsible for MOVPE growth and fabrication of III-V nano-structures on Si. Part of the TFET project (Steeper, E2Switch).

 

2012 February to May, Lund Institute of Technology, Researcher

Responsible for III-V growth, nanowire growth, XRD characterization.

 

2007-2012 Jan, Lund University, Doctoral Researcher

Responsible for own research on Sb-based materials and TFETs. Part of InAs nanowire MOSFET project, InGaAs MOSFET project. Roughly one year devoted to teaching in undergraduate courses

 

2003-2006, Lund University, Student lab supervisor

Supervising lab sessions inundergraduate computer science courses.

 

Education

2007-2012, Doctor of Engineering, Lund University, Sweden

Thesis:”Antimonide Heterostructure Nanowires – Growth, Physics and Devices”, Institution of Physics, Department of Solid State Physics

Supervisor: Professor Lars-Erik Wernersson

 

2006, Master of Science, Lund University, Sweden

”UHV-CVD of SiGe Esaki diodes”, Institution of Physics, 
Department of Solid State Physics

Supervisor: Professor Lars-Erik Wernersson

2002-2006, Civil Engineer in Engineering Physics, Lund University, Sweden

Graduated with high grades (4.6 of 5), focusing studies on Solid State Physics and Computer Science.

Recent Accomplishments and Commitments

  • Operating Manager, Horizon 2020 project INSIGHT
  • Associate Editor, IEEE Transactions of Nanotechnology (Since 2015)
  • Co-inventor of a CMOS-compatible III-V integration method, called Template-Assisted Selective Epitaxy (TASE), with which for the first time was demonstrated highly-controlled vertical nanowire growth on Si(100) substrates, and horizontal III-V finFETs on SOI. This break-through technology opens up the possibility for high-speed III-V devices integrated with Si CMOS.
  • Published a review paper on antimonide nanowire growth, thus summarizing the status of the field and setting the direction for future research.

Grants

The following are research proposals that I co-authored and were successfully funded.

  • 2015 - Horizon 2020 EU-project INSIGHT: (4.2M€)
    III-V nanowire CMOS for RF applications
  • 2013 - FP7 EU-project E2Switch (6.2M€)
    High-performance tunnel field-effect transistors for low-power electronics
  • 2014 - Horizon 2020 EU-project NanoTandem: (4.3M€)
    Integration of nanowire solar cells with Si photovoltaics
  • 2014 - Swiss National Science Foundation: (2 PhD positions) 
    Growth of III-V nanostructures in 3D templates and their characterization

Awards

2nd price for Best Student Contribution at the conference ICMOVPE-XIV in Metz, France 2008 for the paper: Characterization of GaSb nanowires grown by MOVPE